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A.2 Performance Characterization Rules

A.3 DMA Rules

Performance Characterization Rules

Rule 25 — All C6x algorithms must be supplied in little-endian format. (See Section 5.3.1 )

Rule 26 — All C6x algorithms must access all static and global data as far data. (See Section 5.3.2 )

Rule 27 — C6x algorithms must never assume placement in on-chip program memory; i.e., they must

properly operate with program memory operated in cache mode. (See Section 5.3.3 )

Rule 28 — On processors that support large program model compilation, all function accesses to

independently relocatable object modules must be far references. For example, intersection

function references within algorithm and external function references to other

eXpressDSP-compliant modules must be far on the C54x; i.e., the calling function must push both

the XPC and the current PC. (See Section 5.4.2 )

Rule 29 — On processors that support large program model compilation, all independently relocatable

object module functions must be declared as far functions; for example, on the C54x, callers must

push both the XPC and the current PC and the algorithm functions must perform a far return. (See

Section 5.4.2 )

Rule 30 — On processors that support an extended program address space (paged memory), the code

size of any independently relocatable object module should never exceed the code space available

on a page when overlays are enabled. (See Section 5.4.2 )

Rule 31 — All C55x algorithms must document the content of the stack configuration register that they

follow. (See Section 5.5.1 )

Rule 32 — All C55x algorithms must access all static and global data as far data; also the algorithms

should be instantiable in a large memory model. (See Section 5.5.2 )

Rule 33 — C55x algorithms must never assume placement in on-chip program memory; i.e., they must

properly operate with program memory operated in instruction cache mode. (See Section 5.5.3 )

Rule 34 — All C55x algorithms that access data by B-bus must document: the instance number of the

IALG_MemRec structure that is accessed by the B-bus (heap-data), and the data-section name

that is accessed by the B-bus (static-data). (See Section 5.5.4 )

Rule 35 — All TMX320C28x algorithms must access all static and global data as far data; also, the

algorithm should be instantiable in a large memory model. (See Section 5.7.1 )

Rule 19 — All algorithms must characterize their worst-case heap data memory requirements (including

alignment). (See Section 4.1.1 )

Rule 20 — All algorithms must characterize their worst-case stack space memory requirements (including

alignment). (See Section 4.1.2 )

Rule 21 — Algorithms must characterize their static data memory requirements. (See Section 4.1.3 )

Rule 22 — All algorithms must characterize their program memory requirements. (See Section 4.2 )

Rule 23 — All algorithms must characterize their worst-case interrupt latency for every operation. (See

Section 4.3 )

Rule 24 — All algorithms must characterize the typical period and worst-case execution time for each

operation. (See Section 4.4.2 )

DMA Rule 1 — All data transfer must be completed before return to caller. (See Section 6.6 )

DMA Rule 2 — All algorithms using the DMA resource must implement the IDMA2 interface. (See

Section 6.7 )

SPRU352G – June 2005 – Revised February 2007 Rules and Guidelines 77

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Texas Instruments TMS320 DSP User Manual Page 77

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