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6.7 Abstract Interface
Abstract Interface
DMA Guideline 1
The data transfer should complete before the CPU operations executing in parallel.
However, we can never guarantee that the data transfers are complete before data are accessed by the
CPU, even if the algorithm is designed in such a way (e.g., future increase in CPU speed and not DMA
transfer rate). However, since it is important that the data transfer completes before accessing the data to
ensure accurate execution of the algorithm, we have provided two ways to synchronize the methods of
transfer and data access.
• The algorithm can call the ACPY2_complete() runtime API to check if all data transfers on a particular
logical channel have completed.
• The algorithm can call the ACPY2_wait() runtime API to wait for all data transfers on a particular
logical channel to complete. When using the ACPY2 library with IDMA2 interfaces, the algorithms can
call the ACPY2_complete() runtime API to check if all data transfers on a particular logical channel
have completed
After an algorithm returns to the caller from a framework-callable function, the client of the algorithm is free
to move all its memory to a different location and share its scratch memory following the rules in the IALG
interface. It is important that data transfers do not occur across functions that can be called by the client to
avoid a situation where the DMA is transferring data and the framework is moving the locations of the
buffers at the same time.
DMA Rule 1
All data transfer must be completed before return to caller.
When using the ACPY2 library, the algorithm can use the ACPY2_complete() or ACPY2_wait() APIs to
ensure that all data transfers have completed before returning to the caller.
For example, an algorithm can not start a data transfer in algActivate() by calling ACPY2_start() or
ACPY2_startAligned() and then check for completion of the data transfer in the algorithm's "process"
function by calling ACPY2_complete(), or wait for the completion by calling ACPY2_wait().The algorithm
must ensure the data transfer is complete in a algActivate() by using either the ACPY2_complete() or
the ACPY2_wait() API.
Note: Similar to the above-mentioned ACPY2 APIs, the ACPY3 library mentioned in Using DMA with
Framework Components for C64x+ (SPRAAG1) can be used by algorithms that implement the IDMA3
interfaces, to request DMA services from the C64x+ EDMA3 controller. However, unlike the ACPY2
library, the use of the ACPY3 library is NOT mandatory with the IDMA3 interfaces.
eXpressDSP-compliant algorithms are modules that implement the abstract interface IALG. Algorithms
that want to utilize the DMA resource must implement the abstract interface IDMA2 or IDMA3. This means
that the module must declare and initialize a structure of type IDMA2_Fxns, the structure must have a
global scope, its name must follow the uniform naming conventions, and the structure must be declared in
the header file included with the module's library.
The algorithm producer implements the IDMA2 or IDMA3 interface to declare the algorithm's DMA
resource requirement. The algorithm's client calls this interface to get the resource requirement, grant
resources, and change resources at runtime.
DMA Rule 2
All algorithms using the DMA resource must implement the IDMA2 or IDMA3 interface.
All eXpressDSP-compliant algorithms support both run-time and design-time creation of algorithm objects.
To optimize with regards to code space for design-time object creation, it is important that all methods
defined by the IDMA2 or IDMA3 interface are independently relocatable.
SPRU352G – June 2005 – Revised February 2007 Use of the DMA Resource 65
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- User's Guide 1
- Submit Documentation Feedback 2
- Contents 3
- Read This First 7
- Related Documentation 8
- Text Conventions 8
- Overview 9
- 1.1 Scope of the Standard 10
- 1.1.1 Rules and Guidelines 11
- 1.3 Goals of the Standard 12
- 1.4 Intentional Omissions 12
- 1.5 System Architecture 13
- 1.5.1 Frameworks 13
- 1.5.2 Algorithms 14
- 1.5.3 Core Run-Time Support 14
- Chapter 2 15
- 2.1 Use of C Language 16
- 2.2 Threads and Reentrancy 16
- 2.2.1 Threads 16
- 2.2.3 Reentrancy 17
- 2.2.4 Example 18
- 2.3 Data Memory 19
- 2.3.1 Memory Spaces 20
- Data Memory 21
- 2.4 Program Memory 23
- 2.5 ROM-ability 23
- 2.6 Use of Peripherals 24
- Algorithm Component Model 25
- 3.1 Interfaces and Modules 26
- 3.1.1 External Identifiers 27
- 3.1.2 Naming Conventions 28
- 3.1.4 Module Instance Objects 28
- Interfaces and Modules 29
- 3.1.7 Module Configuration 30
- 3.1.8 Example Module 30
- 3.1.10 Interface Inheritance 32
- 3.1.11 Summary 32
- 3.2 Algorithms 33
- 3.3 Packaging 34
- 3.3.1 Object Code 34
- 3.3.2 Header Files 35
- 3.3.3 Debug Verses Release 35
- Packaging 36
- Chapter 4 37
- 4.1 Data Memory 38
- 4.1.1 Heap Memory 38
- 4.1.2 Stack Memory 39
- 4.2 Program Memory 40
- 4.3 Interrupt Latency 41
- 4.4 Execution Time 41
- 4.4.1 MIPS Is Not Enough 41
- 4.4.2 Execution Time Model 42
- Execution Time 43
- DSP-Specific Guidelines 45
- 5.1 CPU Register Types 46
- 5.2 Use of Floating Point 47
- 5.3.1 Endian Byte Ordering 47
- 5.3.2 Data Models 47
- 5.3.3 Program Model 47
- 5.3.4 Register Conventions 48
- 5.3.5 Status Register 48
- 5.3.6 Interrupt Latency 49
- 5.4.1 Data Models 49
- 5.4.2 Program Models 49
- 5.4.3 Register Conventions 51
- 5.4.4 Status Registers 51
- 5.4.5 Interrupt Latency 52
- 5.5.1 Stack Architecture 52
- 5.5.2 Data Models 52
- 5.5.3 Program Models 53
- 5.5.4 Relocatability 53
- 5.5.5 Register Conventions 54
- 5.5.6 Status Bits 55
- 5.6 TMS320C24xx Guidelines 57
- 5.6.1 General 57
- 5.6.2 Data Models 57
- 5.6.3 Program Models 57
- 5.6.4 Register Conventions 57
- 5.6.5 Status Registers 58
- 5.6.6 Interrupt Latency 58
- 5.7.1 Data Models 58
- 5.7.2 Program Models 59
- 5.7.3 Register Conventions 59
- 5.7.4 Status Registers 59
- 5.7.5 Interrupt Latency 60
- Use of the DMA Resource 61
- 6.1 Overview 62
- 6.2 Algorithm and Framework 62
- 6.4 Logical Channel 63
- 6.5 Data Transfer Properties 64
- 6.7 Abstract Interface 65
- 6.8 Resource Characterization 66
- 6.9 Runtime APIs 67
- 6.15.1 Non-Preemptive System 71
- 6.15.3 Preemptive System 72
- Rules and Guidelines 75
- A.1 General Rules 76
- A.3 DMA Rules 77
- A.4 General Guidelines 78
- A.5 DMA Guidelines 79
- Core Run-Time APIs 81
- Bibliography 83
- Glossary 85
- Glossary of Terms 86
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