Texas Instruments TMS320 DSP User Manual Page 49
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5.3.6 Interrupt Latency
5.4 TMS320C54xx Rules and Guidelines
5.4.1 Data Models
5.4.2 Program Models
TMS320C54xx Rules and Guidelines
CSR Field Use Type
EN Current CPU endian mode. Read-only (global)
PWRD Power-Down modes Not accessible (global)
PCC Program Cache Control Not accessible (global)
DCC Data Cache Control. Not accessible (global)
Note that the GIE and PGIE are read-only registers. Algorithms that need to create non-interruptible
sections must use the DSP/BIOS operations HWI_disable() and HWI_restore(). They must never directly
manipulate the GIE or PGIE bits.
Although there are no additional rules for C6x algorithms that deal with interrupt latency, it is important to
note that all instructions in the delay slots of branches are non-interruptible; i.e., once fetched, interrupts
are blocked until the branch completes. Since these delay slots may contain other branch instructions,
care must be taken to avoid long chains of non-interruptible instructions. In particular, tightly coded loops
often result in unacceptably long non-interruptible sequences.
Note that the C compiler has options to limit the duration of loops. Even if this option is used, you must be
careful to limit the length of loops whose length is not a simple constant.
This section describes the rules and guidelines that are specific to the TMS320C5400 family of DSPs.
The C54x has just one data model, so there are no special data memory requirements for this processor.
Some variants of the TMS320C54xx support an extended program address space. Since code can be
compiled for either standard or extended (near or far) addresses, it is possible to have incompatible
mixtures of code.
We need to ensure that calls made from an algorithm to external support functions will be compatible, and
that calls made from the application to an algorithm will be compatible. We also need to ensure that calls
to independently relocatable object modules within an algorithm will be compatible.
Rule 28
On processors that support large program model compilation, all function accesses to independently
relocatable object modules must be far references. For example, intersection function references within
algorithm and external function references to other eXpressDSP-compliant modules must be far on the
C54x; i.e., the calling function must push both the XPC and the current PC.
Rule 29
On processors that support large program model compilation, all independently relocatable object
module functions must be declared as far functions; for example, on the C54x, callers must push both
the XPC and the current PC and the algorithm functions must perform a far return.
This requires that the top-level interface to the algorithm functions be declared as "far." Note that function
calls within the algorithm may be near calls. Still, calls within the algorithm to independently relocatable
object modules must be far calls, since any relocatable object module may be loaded in a 'far' page of
memory.
What about existing applications that do not support far calls to algorithms? Note that it is possible for an
existing application to do a near call into a far algorithm; create a small "near stub" that the application
calls using a near call, the stub then does the appropriate far call and a near return to the application.
SPRU352G – June 2005 – Revised February 2007 DSP-Specific Guidelines 49
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- User's Guide 1
- Submit Documentation Feedback 2
- Contents 3
- Read This First 7
- Related Documentation 8
- Text Conventions 8
- Overview 9
- 1.1 Scope of the Standard 10
- 1.1.1 Rules and Guidelines 11
- 1.3 Goals of the Standard 12
- 1.4 Intentional Omissions 12
- 1.5 System Architecture 13
- 1.5.1 Frameworks 13
- 1.5.2 Algorithms 14
- 1.5.3 Core Run-Time Support 14
- Chapter 2 15
- 2.1 Use of C Language 16
- 2.2 Threads and Reentrancy 16
- 2.2.1 Threads 16
- 2.2.3 Reentrancy 17
- 2.2.4 Example 18
- 2.3 Data Memory 19
- 2.3.1 Memory Spaces 20
- Data Memory 21
- 2.4 Program Memory 23
- 2.5 ROM-ability 23
- 2.6 Use of Peripherals 24
- Algorithm Component Model 25
- 3.1 Interfaces and Modules 26
- 3.1.1 External Identifiers 27
- 3.1.2 Naming Conventions 28
- 3.1.4 Module Instance Objects 28
- Interfaces and Modules 29
- 3.1.7 Module Configuration 30
- 3.1.8 Example Module 30
- 3.1.10 Interface Inheritance 32
- 3.1.11 Summary 32
- 3.2 Algorithms 33
- 3.3 Packaging 34
- 3.3.1 Object Code 34
- 3.3.2 Header Files 35
- 3.3.3 Debug Verses Release 35
- Packaging 36
- Chapter 4 37
- 4.1 Data Memory 38
- 4.1.1 Heap Memory 38
- 4.1.2 Stack Memory 39
- 4.2 Program Memory 40
- 4.3 Interrupt Latency 41
- 4.4 Execution Time 41
- 4.4.1 MIPS Is Not Enough 41
- 4.4.2 Execution Time Model 42
- Execution Time 43
- DSP-Specific Guidelines 45
- 5.1 CPU Register Types 46
- 5.2 Use of Floating Point 47
- 5.3.1 Endian Byte Ordering 47
- 5.3.2 Data Models 47
- 5.3.3 Program Model 47
- 5.3.4 Register Conventions 48
- 5.3.5 Status Register 48
- 5.3.6 Interrupt Latency 49
- 5.4.1 Data Models 49
- 5.4.2 Program Models 49
- 5.4.3 Register Conventions 51
- 5.4.4 Status Registers 51
- 5.4.5 Interrupt Latency 52
- 5.5.1 Stack Architecture 52
- 5.5.2 Data Models 52
- 5.5.3 Program Models 53
- 5.5.4 Relocatability 53
- 5.5.5 Register Conventions 54
- 5.5.6 Status Bits 55
- 5.6 TMS320C24xx Guidelines 57
- 5.6.1 General 57
- 5.6.2 Data Models 57
- 5.6.3 Program Models 57
- 5.6.4 Register Conventions 57
- 5.6.5 Status Registers 58
- 5.6.6 Interrupt Latency 58
- 5.7.1 Data Models 58
- 5.7.2 Program Models 59
- 5.7.3 Register Conventions 59
- 5.7.4 Status Registers 59
- 5.7.5 Interrupt Latency 60
- Use of the DMA Resource 61
- 6.1 Overview 62
- 6.2 Algorithm and Framework 62
- 6.4 Logical Channel 63
- 6.5 Data Transfer Properties 64
- 6.7 Abstract Interface 65
- 6.8 Resource Characterization 66
- 6.9 Runtime APIs 67
- 6.15.1 Non-Preemptive System 71
- 6.15.3 Preemptive System 72
- Rules and Guidelines 75
- A.1 General Rules 76
- A.3 DMA Rules 77
- A.4 General Guidelines 78
- A.5 DMA Guidelines 79
- Core Run-Time APIs 81
- Bibliography 83
- Glossary 85
- Glossary of Terms 86
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