Texas Instruments TMS320 DSP User Manual Page 1

TMS320 DSP Algorithm StandardRules and GuidelinesUser's GuideLiterature Number: SPRU352GJune 2005 – Revised February 2007

www.ti.com1.1 Scope of the StandardRules for TMS320C2xLevel 1Level 2Level 3Level 4TelecomRules for TMS320C5x Rules for TMS320C6xImaging Audio Automoti

www.ti.com1.1.1 Rules and Guidelines1.2 Requirements of the StandardRequirements of the StandardLevel 3 contains the guidelines for specific families

www.ti.com1.3 Goals of the Standard1.4 Intentional OmissionsGoals of the StandardThis section contains the goals of this standard. While it may not be

www.ti.com1.5 System ArchitectureALGALGALGFrameworkStatusCmdStatusCmdCore run time support1.5.1 FrameworksSystem ArchitectureTo support the ability of

www.ti.com1.5.2 Algorithms1.5.3 Core Run-Time SupportSystem ArchitectureCareful inspection of the various frameworks in use reveals that, at some leve

Chapter 2SPRU352G – June 2005 – Revised February 2007General Programming GuidelinesIn this chapter, we develop programming guidelines that apply to al

www.ti.com2.1 Use of C Language2.2 Threads and Reentrancy2.2.1 ThreadsUse of C LanguageAlmost all recently developed software modules follow these com

www.ti.com2.2.2 Preemptive vs. Non-Preemptive Multitasking2.2.3 ReentrancyThreads and ReentrancyNon-preemptive multitasking relies on each thread to v

www.ti.com2.2.4 Exampleyn+ xn* xn*1)1332xn*2Threads and ReentrancyThe definition of reentrant code often implies that the code does not retain "s

www.ti.com2.3 Data MemoryData Memoryvoid PRE_filter1(int input[], int length, int *z){int I, tmp;for (I = 0; I< length; I++) {tmp = input[i] - z[0]

2 SPRU352G – June 2005 – Revised February 2007Submit Documentation Feedback

www.ti.com2.3.1 Memory Spaces2.3.2 Scratch versus PersistentData MemoryWhile the amount of on-chip data memory may be adequate for each algorithm in i

www.ti.comScratchAlgorithm AScratchAlgorithm BWrite-Once CScratchAlgorithm CScratchPhysicalMemoryPersistent BPersistent APersistent A Persistent B Wri

www.ti.com2.3.3 Algorithm versus ApplicationPersistentScratchShared PrivateShadowData MemoryGuideline 1Algorithms should minimize their persistent dat

www.ti.com2.4 Program Memory2.5 ROM-abilityProgram MemoryLike the data memory requirements described in the previous section, it is important that all

www.ti.com2.6 Use of PeripheralsUse of PeripheralsRule 5Algorithms must characterize their ROM-ability; i.e., state whether or not they are ROM-able.O

Chapter 3SPRU352G – June 2005 – Revised February 2007Algorithm Component ModelIn this chapter, we develop additional rules and guidelines that apply t

www.ti.com3.1 Interfaces and Modulesclient.c#include <fir.h> ...FIR_apply();}fir.htypedef struct FIR_obj *FIR_Handle;extern void FIR_init();ext

www.ti.com3.1.1 External IdentifiersInterfaces and ModulesRule 7All header files must support multiple inclusions within a single source file.The gene

www.ti.com3.1.2 Naming Conventions3.1.3 Module Initialization and Finalization3.1.4 Module Instance ObjectsInterfaces and ModulesTo simplify the way e

www.ti.comFIR_Config FIR;FIR_init();FIR_exit();FIR_create();FIRfirObjectCreates firObjectFIRFIR_create();CreatesfirObjectInt length;Int coeff[];Int de

ContentsPreface ... 71 Ove

www.ti.com3.1.7 Module Configuration3.1.8 Example ModuleInterfaces and ModulesGuideline 4All modules that support object creation should support run-t

www.ti.com3.1.9 Multiple Interface SupportInterfaces and Modulestypedef struct FIR_Obj { /* FIR_Obj definition */int hist[16]; /* previous input value

www.ti.com3.1.10 Interface Inheritance3.1.11 SummaryInterfaces and Modulesmodule's header file defines a concrete interface; the functions define

www.ti.com3.2 AlgorithmsIALGIALG_FxnsFIR_Config FIR;FIR_init();FIR_exit();FIR_Fxcs FIR_IALG;FIRImplementsAlgorithmsElement Description RequiredModule&

www.ti.com3.3 Packaging3.3.1 Object CodePackagingRule 13Each of the IALG methods implemented by an algorithm must be independently relocatable.In prac

www.ti.com3.3.2 Header Files3.3.3 Debug Verses ReleasePackaging<module> is the name of the module (containing characters from the set [a-z0-9]),

www.ti.comPackagingIf multiple versions of the same component are provided by a single vendor, the different versions must bein different libraries (a

Chapter 4SPRU352G – June 2005 – Revised February 2007Algorithm Performance CharacterizationIn this chapter, we examine the performance information tha

www.ti.com4.1 Data Memory4.1.1 Heap MemoryData MemoryThe only resources consumed by eXpressDSP-compliant algorithms are MIPS and memory. All I/O,perip

www.ti.com4.1.2 Stack Memory4.1.3 Static Local and Global Data MemoryData MemoryIn the example above, the algorithm requires 960 16-bit words of singl

4 Algorithm Performance Characterization ... 374.1 Data Memory...

www.ti.com4.2 Program MemoryProgram MemoryAlgorithms must characterize their static data memory requirements by filling out a table such as thatillust

www.ti.com4.3 Interrupt Latency4.4 Execution Time4.4.1 MIPS Is Not EnoughInterrupt LatencyCodeCode Sections Size Aligna.obj(.text) 768 0b.obj(.text) 1

www.ti.com3 ms 3 ms 3 ms 3 msABIdle4.4.2 Execution Time ModelExecution TimeFigure 4-1. Execution Timeline for Two Periodic TasksIn this case, both tas

www.ti.comExecution TimeExecution time should be expressed in instruction cycles whereas the period expressed in microseconds.Worst-case execution tim

www.ti.comAlgorithm Performance Characterization44 SPRU352G – June 2005 – Revised February 2007Submit Documentation Feedback

Chapter 5SPRU352G – June 2005 – Revised February 2007DSP-Specific GuidelinesThis chapter provides guidelines for creating eXpressDSP-compliant algorit

www.ti.com5.1 CPU Register TypesRead−only Scratch PreserveInitGlobalLocalRead−writeCPU Register TypesDSP algorithms are often written in assembly lang

www.ti.com5.2 Use of Floating Point5.3 TMS320C6xxx Rules and Guidelines5.3.1 Endian Byte Ordering5.3.2 Data Models5.3.3 Program ModelUse of Floating P

www.ti.com5.3.4 Register Conventions5.3.5 Status RegisterTMS320C6xxx Rules and GuidelinesIn addition, no algorithm may ever directly manipulate the ca

www.ti.com5.3.6 Interrupt Latency5.4 TMS320C54xx Rules and Guidelines5.4.1 Data Models5.4.2 Program ModelsTMS320C54xx Rules and GuidelinesCSR Field Us

6.2 Algorithm and Framework ... 626.3 Requirements for the Use of

www.ti.comTMS320C54xx Rules and GuidelinesThere are, of course, cases where it would be desirable that the core run-time support is accessible withnea

www.ti.com5.4.3 Register Conventions5.4.4 Status RegistersTMS320C54xx Rules and GuidelinesThis section describes the rules and guidelines that apply t

www.ti.com5.4.5 Interrupt Latency5.5 TMS320C55x Rules and Guidelines5.5.1 Stack Architecture5.5.2 Data ModelsTMS320C55x Rules and GuidelinesST1 Field

www.ti.com5.5.3 Program Models5.5.4 RelocatabilityTMS320C55x Rules and GuidelinesRule 32All C55x algorithms must access all static and global data as

www.ti.com5.5.5 Register ConventionsTMS320C55x Rules and GuidelinesIf the algorithm does not use B-bus, then the first column must be zero. If there i

www.ti.com5.5.6 Status BitsTMS320C55x Rules and GuidelinesThe C55xx contains four status registers: ST0, ST1, ST2 and ST3.ST0 Field Name Use TypeACOV2

www.ti.comTMS320C55x Rules and GuidelinesST3 Field Name Use TypeHOMY Host only access mode Read-only (global)HOMX Host only access mode Read-only (glo

www.ti.com5.6 TMS320C24xx Guidelines5.6.1 GeneralTMS320 DSP Standard Algorithms vs. DCS Modules The C24xx family of DSPsare classified as DSP controll

www.ti.com5.6.5 Status Registers5.6.6 Interrupt Latency5.7 TMS320C28x Rules and Guidelines5.7.1 Data ModelsTMS320C28x Rules and GuidelinesRegister Use

www.ti.com5.7.2 Program Models5.7.3 Register Conventions5.7.4 Status RegistersTMS320C28x Rules and GuidelinesOnly large memory model is supported for

List of Figures1-1 TMS320 DSP Algorithm Standard Elements ... 101-2 DSP Softwa

www.ti.com5.7.5 Interrupt LatencyTMS320C28x Rules and GuidelinesST1 Field Name Use TypeARP Auxiliary register pointer Scratch (local)XF XF pin status

Chapter 6SPRU352G – June 2005 – Revised February 2007Use of the DMA ResourceThe direct memory access (DMA) controller performs asynchronously schedule

www.ti.com6.1 Overview6.2 Algorithm and FrameworkOverviewRule 6 states that "Algorithms must never directly access any peripheral device. This in

www.ti.com6.3 Requirements for the Use of the DMA Resource6.4 Logical ChannelRequirements for the Use of the DMA Resourcethrough the logical DMA chann

www.ti.com6.5 Data Transfer PropertiesElem0 Elem1 Elem2 Elem3Gaps betweenelementsElement indexFrameElement sizeFrame 0Frame 1Frame N-1Number offrames

www.ti.com6.7 Abstract InterfaceAbstract InterfaceDMA Guideline 1The data transfer should complete before the CPU operations executing in parallel.How

www.ti.com6.8 Resource CharacterizationResource CharacterizationDMA Rule 3Each of the IDMA2 or IDMA3 methods implemented by an algorithm must be indep

www.ti.com6.9 Runtime APIs6.10 Strong Ordering of DMA Transfer RequestsRuntime APIsFor example, in the table above, the "process" operation

www.ti.com6.11 Submitting DMA Transfer Requests6.12 Device Independent DMA Optimization GuidelineSubmitting DMA Transfer RequestsThe specification of

www.ti.com6.13 C6xxx Specific DMA Rules and Guidelines6.13.1 Cache Coherency Issues for Algorithm ProducersYX = 0ldY = newXL2 cache External memoryDMA

PrefaceSPRU352G – June 2005 – Revised February 2007Read This FirstThis document defines a set of requirements for DSP algorithms that, if followed, al

www.ti.comVX = 0ldY = newVXL2 cache External memoryYDMACache line6.14 C55x Specific DMA Rules and Guidelines6.14.1 Supporting Packed/Burst Mode DMA Tr

www.ti.com6.14.2 Minimizing Logical Channel Reconfiguration Overhead6.14.3 Addressing Automatic Endianism Conversion Issues6.15 Inter-Algorithm Synchr

www.ti.comDMA/CPU idleCPU context switchCPU/DMA activeAlgorithm AactiveAlgorithm BactiveCPU context(timeline)DMA context(timeline)1 2 3 4 56.15.3 Pree

www.ti.comDMA/CPU idleCPU context switchCPU/DMA activeAlgorithm AactiveAlgorithm Bactive activeAlgorithm ACPU context(timeline)DMA context(timeline)1

www.ti.comInter-Algorithm SynchronizationIt is important to notice that preemptive systems might have groups of algorithms that execute with thesame p

Appendix ASPRU352G – June 2005 – Revised February 2007Rules and GuidelinesThis appendix gathers together all rules and guidelines into one compact ref

www.ti.comA.1 General RulesGeneral RulesRecall that rules must be followed in order for software to be eXpressDSP-compliant. Guidelines, on theother h

www.ti.comA.2 Performance Characterization RulesA.3 DMA RulesPerformance Characterization RulesRule 25 — All C6x algorithms must be supplied in little

www.ti.comA.4 General GuidelinesGeneral GuidelinesDMA Rule 3 — Each of the IDMA2 methods implemented by an algorithm must be independentlyrelocateable

www.ti.comA.5 DMA GuidelinesDMA GuidelinesGuideline 12 — All C6x algorithms should be supplied in both little- and big-endian formats. (SeeSection 5.3

www.ti.comRelated Documentation• Chapter 6 - Use of the DMA Resource, develops guidelines and rules for creatingeXpressDSP-compliant algorithms that u

www.ti.comRules and Guidelines80 SPRU352G – June 2005 – Revised February 2007Submit Documentation Feedback

Appendix BSPRU352G – June 2005 – Revised February 2007Core Run-Time APIsThis appendix enumerates all acceptable core run-time APIs that may be referen

www.ti.comB.1 TI C-Language Run-Time Support LibraryB.2 DSP/BIOS Run-time Support LibraryTI C-Language Run-Time Support LibraryRecall that only a subs

C.1 BooksC.2 URLSAppendix CSPRU352G – June 2005 – Revised February 2007BibliographyThis appendix lists sources for additional information.Dialogic, Me

www.ti.comBibliography 84 SPRU352G – June 2005 – Revised February 2007Submit Documentation Feedback

D.1 Glossary of TermsAppendix DSPRU352G – June 2005 – Revised February 2007GlossaryAbstract Interface — An interface defined by a C header whose funct

www.ti.comGlossary of TermsEndian — Refers to which bytes are most significant in multi-byte data types. In big-endian architectures,the leftmost byte

www.ti.comGlossary of TermsScheduling — The process of deciding what thread should execute next on a particular CPU. It is usuallyalso taken as involv

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improve

Chapter 1SPRU352G – June 2005 – Revised February 2007OverviewThis chapter provides an overview of the TMS320 DSP Algorithm Standard.Topic ....