Texas-instruments MSP430x4xx User Manual

  2005 Mixed Signal ProductsUser’s GuideSLAU056E

Contentsx11 Basic Timer1 11-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Set3-66 RISC 16−Bit CPUSUB[.W] Subtract source from destinationSUB.B Subtract source from destinationSyntax SUB src,dst or SUB.W src,dstS

Instruction Set3-67 RISC 16−Bit CPUSUBC[.W]SBB[.W] Subtract source and borrow/.NOT. carry from destinationSUBC.B,SBB.B Subtract source and borrow/

Instruction Set3-68 RISC 16−Bit CPUSWPB Swap bytesSyntax SWPB dstOperation Bits 15 to 8 <−> bits 7 to 0Description The destination operand high

Instruction Set3-69 RISC 16−Bit CPUSXT Extend SignSyntax SXT dstOperation Bit 7 −> Bit 8 ... Bit 15Description The sign of the low byte is e

Instruction Set3-70 RISC 16−Bit CPU* TST[.W] Test destination* TST.B Test destinationSyntax TST dst or TST.W dstTST.B dstOperation dst + 0FFFFh + 1dst

Instruction Set3-71 RISC 16−Bit CPUXOR[.W] Exclusive OR of source with destinationXOR.B Exclusive OR of source with destinationSyntax XOR src,dst or

Instruction Set3-72 RISC 16−Bit CPU3.4.4 Instruction Cycles and LengthsThe number of CPU clock cycles required for an instruction depends on theinstru

Instruction Set3-73 RISC 16−Bit CPUFormat-I (Double Operand) Instruction Cycles and LengthsTable 3−16 lists the length and CPU cycles for all address

Instruction Set3-74 RISC 16−Bit CPU3.4.5 Instruction Set DescriptionThe instruction map is shown in Figure 3−20 and the complete instruction setis sum

Instruction Set3-75 RISC 16−Bit CPUTable 3−17.MSP430 Instruction SetMnemonic Description V N Z CADC(.B)†dst Add C to destination dst + C → dst * * *

Contentsxi 15 USART Peripheral Interface, SPI Mode 15-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1 USART

4-1FLL+ Clock Module   The FLL+ clock module provides the clocks for MSP430x4xx devices. Thischapter discusses the FLL+ clock module.

4-2 FLL+ Clock Module4.1 FLL+ Clock Module IntroductionThe frequency-locked loop (FLL+) clock module supports low system cost andultralow-power consum

4-3FLL+ Clock ModuleFigure 4−1. MSP430x44x and MSP430x43x Frequency-Locked Loop10−bitFrequencyIntegratorDCO+ModulatorDCGeneratorOSCOFFFNxSCG1offSCG0En

4-4 FLL+ Clock ModuleFigure 4−2. MSP430x42x and MSP430x41x Frequency-Locked Loop10−bitFrequencyIntegratorDCO+ModulatorDCGeneratorOSCOFFFNxSCG1offSCG0E

FLL+ Clock Module Operation4-5FLL+ Clock Module4.2 FLL+ Clock Module OperationAfter a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times theACLK

FLL+ Clock Module Operation4-6 FLL+ Clock Module4.2.2 LFXT1 OscillatorThe LFXT1 oscillator supports ultralow-current consumption using a32,768-Hz watc

FLL+ Clock Module Operation4-7FLL+ Clock Module4.2.4 Digitally-Controlled Oscillator (DCO)The DCO is an integrated ring oscillator with RC-type charac

FLL+ Clock Module Operation4-8 FLL+ Clock Module4.2.6 DCO ModulatorThe modulator mixes two adjacent DCO frequencies to produce anintermediate effectiv

FLL Operation from Low-Power Modes-4-9FLL+ Clock Module4.2.7 Disabling the FLL Hardware and ModulatorThe FLL is disabled when the status register bit

Buffered Clock Output4-10 FLL+ Clock Module4.2.10 FLL+ Fail-Safe OperationThe FLL+ module incorporates an oscillator-fault fail-safe feature. This fea

Contentsxii19 LCD_A Controller 19-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FLL+ Clock Module Registers4-11FLL+ Clock Module4.3 FLL+ Clock Module RegistersThe FLL+ registers are listed in Table 4−2.Table 4−2.FLL+ RegistersRegi

FLL+ Clock Module Registers4-12 FLL+ Clock ModuleSCFQCTL, System Clock Control Register76543210SCFQ_M Nrw−0 rw−0 rw−0 rw−1 rw−1 rw−1 rw−1 rw−1SCFQ_MBi

FLL+ Clock Module Registers4-13FLL+ Clock ModuleSCFI1, System Clock Frequency Integrator Register 176543210DCOx MODx (MSBs) rw−0 rw−0 rw−0 rw−0 rw−0

FLL+ Clock Module Registers4-14 FLL+ Clock ModuleFLL_CTL0, FLL+ Control Register 076543210DCOPLUS XTS_FLL XCAPxPF XT2OF†XT1OF LFOF DCOFrw−0 rw−0 rw−0

FLL+ Clock Module Registers4-15FLL+ Clock ModuleFLL_CTL1, FLL+ Control Register 176543210UnusedSMCLKOFF†XT2OFF†SELMx†SELS†FLL_DIVxr0 r0 rw−(1) rw−(0)

FLL+ Clock Module Registers4-16 FLL+ Clock ModuleIE1, Interrupt Enable Register 176543210OFIErw−0Bits7-2These bits may be used by other modules. See d

5-1 Flash Memory Controller   This chapter describes the operation of the MSP430 flash memory controller.Topic Page5.1 Flash

Flash Memory Introduction5-2 Flash Memory Controller5.1 Flash Memory IntroductionThe MSP430 flash memory is bit-, byte-, and word-addressable andprog

Flash Memory Segmentation5-3 Flash Memory Controller5.2 Flash Memory SegmentationMSP430 flash memory is partitioned into segments. Single bits, bytes,

Flash Memory Operation5-4 Flash Memory Controller5.3 Flash Memory OperationThe default mode of the flash memory is read mode. In read mode, the flash

Contentsxiii 22 SD16_A 22-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flash Memory Operation5-5 Flash Memory Controller5.3.2 Erasing Flash MemoryThe erased level of a flash memory bit is 1. Each bit can be programmed fro

Flash Memory Operation5-6 Flash Memory ControllerInitiating an Erase from Within Flash MemoryAny erase cycle can be initiated from within flash memor

Flash Memory Operation5-7 Flash Memory ControllerInitiating an Erase from RAMAny erase cycle may be initiated from RAM. In this case, the CPU is not h

Flash Memory Operation5-8 Flash Memory Controller5.3.3 Writing Flash MemoryThe write modes, selected by the WRT and BLKWRT bits, are listed inTable 5

Flash Memory Operation5-9 Flash Memory ControllerIn byte/word mode, the internally-generated programming voltage is appliedto the complete 64-byte blo

Flash Memory Operation5-10 Flash Memory ControllerInitiating a Byte/Word Write from RAMThe flow to initiate a byte/word write from RAM is shown in Fi

Flash Memory Operation5-11 Flash Memory ControllerBlock WriteThe block write can be used to accelerate the flash write process when manysequential byt

Flash Memory Operation5-12 Flash Memory ControllerBlock Write Flow and ExampleA block write flow is shown in Figure 5−8 and the following example.Fig

Flash Memory Operation5-13 Flash Memory Controller; Write one block starting at 0F000h.; Must be executed from RAM, Assumes Flash is already erased.;

Flash Memory Operation5-14 Flash Memory Controller5.3.4 Flash Memory Access During Write or EraseWhen any write or any erase operation is initiated f

1-1Introduction IntroductionThis chapter describes the architecture of the MSP430.Topic Page1.1 Architecture 1-2. . . . . . . . . . . . . . . . . . .

Flash Memory Operation5-15 Flash Memory Controller5.3.5 Stopping a Write or Erase CycleAny write or erase operation can be stopped before its normal c

Flash Memory Operation5-16 Flash Memory ControllerProgramming Flash Memory via JTAGMSP430 devices can be programmed via the JTAG port. The JTAG inter

Flash Memory Registers5-17 Flash Memory Controller5.4 Flash Memory RegistersThe flash memory registers are listed in Table 5−4.Table 5−4.Flash Memory

Flash Memory Registers5-18 Flash Memory ControllerFCTL1, Flash Memory Control Register15 14 13 12 11 10 9 8FRKEY, Read as 096hFWKEY, Must be written

Flash Memory Registers5-19 Flash Memory ControllerFCTL2, Flash Memory Control Register15 14 13 12 11 10 9 8FWKEYx, Read as 096hMust be written as 0A5h

Flash Memory Registers5-20 Flash Memory ControllerFCTL3, Flash Memory Control Register FCTL315 14 13 12 11 10 9 8FWKEYx, Read as 096hMust be written

Flash Memory Registers5-21 Flash Memory ControllerIE1, Interrupt Enable Register 176543210ACCVIErw−0Bits7-6,4-0These bits may be used by other modules

6-1Supply Voltage Supervisor   This chapter describes the operation of the SVS. The SVS is implemented inall MSP430x4x device

SVS Introduction6-2 Supply Voltage Supervisor6.1 SVS IntroductionThe supply voltage supervisor (SVS) is used to monitor the AVCC supplyvoltage or an e

SVS Introduction6-3Supply Voltage SupervisorFigure 6−1. SVS Block Diagram+− 1.25VBrownoutResetVCCSet SVSFGtReset ~ 50usResetSVSCTL Bits000100100011111

Architecture1-2 Introduction1.1 ArchitectureThe MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clocksystem that interconnect using

SVS Operation6-4 Supply Voltage Supervisor6.2 SVS OperationThe SVS detects if the AVCC voltage drops below a selectable level. It can beconfigured to

SVS Operation6-5Supply Voltage Supervisor6.2.3 Changing the VLDx BitsWhen the VLDx bits are changed, two settling delays are implemented toallows the

SVS Operation6-6 Supply Voltage Supervisor6.2.4 SVS Operating RangeEach SVS level has hysteresis to reduce sensitivity to small supply voltagechanges

SVS Registers6-7Supply Voltage Supervisor6.3 SVS RegistersThe SVS registers are listed in Table 6−1.Table 6−1.SVS RegistersRegister Short Form Registe

7-1Hardware Multiplier Hardware MultiplierThis chapter describes the hardware multiplier. The hardware multiplier isimplemented in MSP430x44x devices.

Hardware Multiplier Introduction7-2 Hardware Multiplier7.1 Hardware Multiplier IntroductionThe hardware multiplier is a peripheral and is not part of

Hardware Multiplier Operation7-3Hardware Multiplier7.2 Hardware Multiplier OperationThe hardware multiplier supports unsigned multiply, signed multipl

Hardware Multiplier Operation7-4 Hardware Multiplier7.2.2 Result RegistersThe result low register RESLO holds the lower 16-bits of the calculation res

Hardware Multiplier Operation7-5Hardware Multiplier7.2.3 Software ExamplesExamples for all multiplier modes follow. All 8x8 modes use the absoluteaddr

Hardware Multiplier Operation7-6 Hardware Multiplier7.2.4 Indirect Addressing of RESLOWhen using indirect or indirect autoincrement addressing mode to

Embedded Emulation1-3IntroductionFigure 1−1. MSP430 ArchitectureACLKBusConv.PeripheralMAB 16-BitMDB 16-BitMCLKSMCLKClockSystemPeripheral PeripheralPer

Hardware Multiplier Registers7-7Hardware Multiplier7.3 Hardware Multiplier RegistersThe hardware multiplier registers are listed in Table 7−4.Table 7−

8-1  The DMA controller module transfers data from one address to anotherwithout CPU intervention. This chapter describes the operation

8-28.1 DMA IntroductionThe direct memory access (DMA) controller transfers data from one addressto another, without CPU intervention, across the entir

8-3Figure 8−1. DMA Controller Block DiagramDMA Priority And ControlENNMIDTDMA Channel 2DMASRSBYTEDMA2SZDMA2DADMA2SADMADSTBYTEDMASRCINCRxDMADSTINCRx223

8-48.2 DMA OperationThe DMA controller is configured with user software. The setup and operationof the DMA is discussed in the following sections.8.2.

8-58.2.2 DMA Transfer ModesThe DMA controller has six transfer modes selected by the DMADTx bits aslisted in Table 8−1. Each channel is individually c

8-6Single TransferIn single transfer mode, each byte/word transfer requires a separate trigger.The single transfer state diagram is shown in Figure 8−

8-7Figure 8−3. DMA Single Transfer State DiagramResetWait for TriggerIdleHold CPU,Transfer one word/byte[+Trigger AND DMALEVEL = 0 ]OR[Trigger=1 AND D

8-8Block TransfersIn block transfer mode, a transfer of a complete block of data occurs after onetrigger. When DMADTx = 1, the DMAEN bit is cleared af

8-9Figure 8−4. DMA Block Transfer State DiagramResetWait for TriggerIdleHold CPU,Transfer one word/byte[+Trigger AND DMALEVEL = 0 ]OR[Trigger=1 AND DM

Address Space1-4 Introduction1.4 Address SpaceThe MSP430 von-Neumann architecture has one address space shared withspecial function registers (SFRs),

8-10Burst-Block TransfersIn burst-block mode, transfers are block transfers with CPU activityinterleaved. The CPU executes 2 MCLK cycles after every f

8-11Figure 8−5. DMA Burst-Block Transfer State Diagram2 x MCLKResetWait for TriggerIdleHold CPU,Transfer one word/byteBurst State(release CPU for 2xMC

8-128.2.3 Initiating DMA TransfersEach DMA channel is independently configured for its trigger source with theDMAxTSELx bits as described in Table 8−2

8-13Table 8−2.DMA Trigger OperationDMAxTSELx Operation0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically resetwh

8-148.2.4 Stopping DMA TransfersThere are two ways to stop DMA transfers in progress:- A single, block, or burst-block transfer may be stopped with an

8-158.2.6 DMA Transfer Cycle TimeThe DMA controller requires one or two MCLK clock cycles to synchronizebefore each single transfer or complete block

8-168.2.7 Using DMA with System InterruptsDMA transfers are not interruptible by system interrupts. System interruptsremain pending until the completi

8-178.2.9 Using the I2C Module with the DMA ControllerThe I2C module provides two trigger sources for the DMA controller. The I2Cmodule can trigger a

8-188.3 DMA RegistersThe DMA registers are listed in Table 8−4.Table 8−4.DMA RegistersRegister Short Form Register Type Address Initial StateDMA contr

8-19DMACTL0, DMA Control Register 015 14 13 12 11 10 9 8ReservedDMA2TSELxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)76543210DMA1TSELx DMA0

Address Space1-5Introduction1.4.3 Peripheral ModulesPeripheral modules are mapped into the address space. The address spacefrom 0100 to 01FFh is reser

8-20DMACTL1, DMA Control Register 115 14 13 12 11 10 9 800 0 0 0 0 0 0r0 r0 r0 r0 r0 r0 r0 r0765432100 0 0 0 0DMAONFETCHROUNDROBINENNMIr0 r0 r0 r0 r0

8-21DMAxCTL, DMA Channel x Control Register15 14 13 12 11 10 9 8ReservedDMADTx DMADSTINCRx DMASRCINCRxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

8-22DMASRCBYTEBit 6 DMA source byte. This bit selects the source as a byte or word.0 Word1 ByteDMALEVELBit 5 DMA level. This bit selects between edge-

8-23DMAxDA, DMA Destination Address Register15 14 13 12 11 10 9 8DMAxDAxrw rw rw rw rw rw rw rw76543210DMAxDAxrw rw rw rw rw rw rw rwDMAxDAx Bits15−0D

9-1Digital I/O Digital I/OThis chapter describes the operation of the digital I/O ports. Ports P1-P6 areimplemented in all MSP430x4xx devices.Topic Pa

Digital I/O Introduction9-2 Digital I/O9.1 Digital I/O IntroductionMSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each porthas ei

Digital I/O Operation9-3Digital I/O9.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of thedigital I

Digital I/O Operation9-4 Digital I/O9.2.4 Function Select Registers PxSELPort pins are often multiplexed with other peripheral module functions. See t

Digital I/O Operation9-5Digital I/O9.2.5 P1 and P2 InterruptsEach pin in ports P1 and P2 have interrupt capability, configured with thePxIFG, PxIE, an

Digital I/O Operation9-6 Digital I/OInterrupt Edge Select Registers P1IES, P2IESEach PxIES bit selects the interrupt edge for the corresponding I/O pi

2-1System Resets, Interrupts, and Operating Modes System Resets, Interrupts,and Operating ModesThis chapter describes the MSP430x4xx system resets, in

Digital I/O Registers9-7Digital I/O9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used toconfigure port

10-1Watchdog Timer, Watchdog Timer+    The watchdog timer is a 16-bit timer that can be used as a watchdog or as aninte

Watchdog Timer Introduction10-2 Watchdog Timer, Watchdog Timer+10.1 Watchdog Timer IntroductionThe primary function of the watchdog timer (WDT) module

Watchdog Timer Introduction10-3Watchdog Timer, Watchdog Timer+Figure 10−1. Watchdog Timer Block DiagramWDTQnY1234Q6Q9Q13Q1516−bitCounterCLKAB11AENPUCS

Watchdog Timer Operation10-4 Watchdog Timer, Watchdog Timer+10.2 Watchdog Timer OperationThe WDT module can be configured as either a watchdog or inte

Watchdog Timer Operation10-5Watchdog Timer, Watchdog Timer+10.2.4 Watchdog Timer InterruptsThe WDT uses two bits in the SFRs for interrupt control.- T

Watchdog Timer Operation10-6 Watchdog Timer, Watchdog Timer+10.2.6 Operation in Low-Power ModesThe MSP430 devices have several low-power modes. Differ

Watchdog Timer Registers10-7Watchdog Timer, Watchdog Timer+10.3 Watchdog Timer RegistersThe watchdog timer module registers are listed in Table 10−1.T

Watchdog Timer Registers10-8 Watchdog Timer, Watchdog Timer+WDTCTL, Watchdog Timer Register15 14 13 12 11 10 9 8Read as 069hWDTPW, must be written as

Watchdog Timer Registers10-9Watchdog Timer, Watchdog Timer+IE1, Interrupt Enable Register 176543210NMIIE WDTIErw−0 rw−0Bits7-5These bits may be used b

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvemen

System Reset and Initialization2-2 System Resets, Interrupts, and Operating Modes2.1 System Reset and InitializationThe system reset circuitry shown i

Watchdog Timer Registers10-10 Watchdog Timer, Watchdog Timer+IFG1, Interrupt Flag Register 176543210NMIIFG WDTIFGrw−(0) rw−(0)Bits7-5These bits may be

11-1Basic Timer1  The Basic Timer1 module is two independent, cascadable 8-bit timers. Thischapter describes the Basic Timer1. Basic Timer

Basic Timer1 Introduction11-2 Basic Timer111.1 Basic Timer1 IntroductionThe Basic Timer1 supplies LCD timing and low frequency time intervals. TheBasi

Basic Timer1 Introduction11-3Basic Timer1Figure 11−1. Basic Timer1 Block DiagramBTCNT2Set_BTIFGBTCNT1EN1CLK1Q4 Q5 Q6 Q7BTDIVBTHOLDACLKEN2CLK2Q4 Q5 Q6

Basic Timer1 Introduction11-4 Basic Timer111.2 Basic Timer1 OperationThe Basic Timer1 module can be configured as two 8-bit timers or one 16-bittimer

Basic Timer1 Introduction11-5Basic Timer111.2.4 Basic Timer1 Operation: Signal fLCDThe LCD controller (but not the LCDA controller) uses the fLCD sign

Basic Timer1 Introduction11-6 Basic Timer111.3 Basic Timer1 RegistersThe watchdog timer module registers are listed in Table 11−1.Table 11−1.Basic Tim

Basic Timer1 Introduction11-7Basic Timer1BTCTL, Basic Timer1 Control Register76543210BTSSEL BTHOLD BTDIV BTFRFQx BTIPxrw rw rw rw rw rw rw rwBTSSELBit

Basic Timer1 Introduction11-8 Basic Timer1BTCNT1, Basic Timer1 Counter 176543210BTCNT1xrw rw rw rw rw rw rw rwBTCNT1xBits7−0BTCNT1 register. The BTCNT

Basic Timer1 Introduction11-9Basic Timer1IE2, Interrupt Enable Register 276543210BTIErw−0BTIEBit 7 Basic Timer1 interrupt enable. This bit enables the

System Reset and Initialization2-3System Resets, Interrupts, and Operating Modes2.1.1 Brownout Reset (BOR)All MSP430x4xx devices have a brownout reset

12-1Timer_A Timer_ATimer_A is a 16-bit timer/counter with multiple capture/compare registers. Thischapter describes Timer_A. Timer_A3 (three capture/c

Timer_A Introduction12-2 Timer_A12.1 Timer_A IntroductionTimer_A is a 16-bit timer/counter with three or five capture/compare registers.Timer_A can su

Timer_A Introduction12-3Timer_AFigure 12−1. Timer_A Block DiagramCCR4Compararator 2CCI15 0CCISxOUTMODxCaptureModeCMxSyncSCSCOVlogicOutputUnit4DSetQEQU

Timer_A Operation12-4 Timer_A12.2 Timer_A OperationThe Timer_A module is configured with user software. The setup andoperation of Timer_A is discussed

Timer_A Operation12-5Timer_A12.2.2 Starting the TimerThe timer may be started, or restarted in the following ways:- The timer counts when MCx > 0 a

Timer_A Operation12-6 Timer_AUp ModeThe up mode is used if the timer period must be different from 0FFFFh counts.The timer repeatedly counts up to the

Timer_A Operation12-7Timer_AContinuous ModeIn the continuous mode, the timer repeatedly counts up to 0FFFFh and restartsfrom zero as shown in Figure 1

Timer_A Operation12-8 Timer_AUse of the Continuous ModeThe continuous mode can be used to generate independent time intervals andoutput frequencies. E

Timer_A Operation12-9Timer_AUp/Down ModeThe up/down mode is used if the timer period must be different from 0FFFFhcounts, and if symmetrical pulse gen

Timer_A Operation12-10 Timer_AChanging the Period Register TACCR0When changing TACCR0 while the timer is running, and counting in the downdirection, t

System Reset and Initialization2-4 System Resets, Interrupts, and Operating Modes2.1.2 Device Initial Conditions After System ResetAfter a POR, the in

Timer_A Operation12-11Timer_A12.2.4 Capture/Compare BlocksThree or five identical capture/compare blocks, TACCRx, are present inTimer_A. Any of the bl

Timer_A Operation12-12 Timer_AFigure 12−11.Capture CycleSecondCaptureTakenCOV = 1CaptureTakenNoCaptureTakenReadTakenCaptureClear Bit COVin Register TA

Timer_A Operation12-13Timer_A12.2.5 Output UnitEach capture/compare block contains an output unit. The output unit is usedto generate output signals s

Timer_A Operation12-14 Timer_AOutput Example—Timer in Up ModeThe OUTx signal is changed when the timer counts up to the TACCRx value,and rolls from TA

Timer_A Operation12-15Timer_AOutput Example—Timer in Continuous ModeThe OUTx signal is changed when the timer reaches the TACCRx andTACCR0 values, dep

Timer_A Operation12-16 Timer_AOutput Example—Timer in Up/Down ModeThe OUTx signal changes when the timer equals TACCRx in either countdirection and wh

Timer_A Operation12-17Timer_A12.2.6 Timer_A InterruptsTwo interrupt vectors are associated with the 16-bit Timer_A module:- TACCR0 interrupt vector fo

Timer_A Operation12-18 Timer_ATAIV Software ExampleThe following software example shows the recommended use of TAIV and thehandling overhead. The TAIV

Timer_A Registers12-19Timer_A12.3 Timer_A RegistersThe Timer_A registers are listed in Table 12−3 and Table 12−4.Table 12−3.Timer_A3 RegistersRegister

Timer_A Registers12-20 Timer_ATACTL, Timer_A Control Register15 14 13 12 11 10 9 8UnusedTASSELxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

System Reset and Initialization2-5System Resets, Interrupts, and Operating Modes2.2 InterruptsThe interrupt priorities are fixed and defined by the ar

Timer_A Registers12-21Timer_ATAR, Timer_A Register15 14 13 12 11 10 9 8TARxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)76543210TARxrw−(0) r

Timer_A Registers12-22 Timer_ATACCTLx, Capture/Compare Control Register15 14 13 12 11 10 9 8CMxCCISx SCS SCCI Unused CAPrw−(0) rw−(0) rw−(0) rw−(0) rw

Timer_A Registers12-23Timer_ACCIEBit 4 Capture/compare interrupt enable. This bit enables the interrupt request ofthe corresponding CCIFG flag.0 Inter

13-1Timer_B Timer_BTimer_B is a 16-bit timer/counter with multiple capture/compare registers. Thischapter describes Timer_B. Timer_B3 (three capture/c

Timer_B Introduction13-2 Timer_B13.1 Timer_B IntroductionTimer_B is a 16-bit timer/counter with three or seven capture/compareregisters. Timer_B can s

Timer_B Introduction13-3Timer_BFigure 13−1. Timer_B Block DiagramCCR6Compararator 6CCI15 0OUTMODxCaptureModeCMxSyncCOVlogicOutputUnit6DSetQEQU0OUTOUT6

Timer_B Operation13-4 Timer_B13.2 Timer_B OperationThe Timer_B module is configured with user software. The setup andoperation of Timer_B is discussed

Timer_B Operation13-5Timer_B13.2.2 Starting the TimerThe timer may be started or restarted in the following ways:- The timer counts when MCx > 0 an

Timer_B Operation13-6 Timer_BUp ModeThe up mode is used if the timer period must be different from TBR(max) counts.The timer repeatedly counts up to t

Timer_B Operation13-7Timer_BContinuous ModeIn continuous mode the timer repeatedly counts up to TBR(max) and restartsfrom zero as shown in Figure 13−4

System Reset and Initialization2-6 System Resets, Interrupts, and Operating Modes2.2.1 (Non)-Maskable Interrupts (NMI)(Non)-maskable NMI interrupts ar

Timer_B Operation13-8 Timer_BUse of the Continuous ModeThe continuous mode can be used to generate independent time intervals andoutput frequencies. E

Timer_B Operation13-9Timer_BUp/Down ModeThe up/down mode is used if the timer period must be different from TBR(max)counts, and if symmetrical pulse g

Timer_B Operation13-10 Timer_BChanging the Value of Period Register TBCL0When changing TBCL0 while the timer is running, and counting in the downdirec

Timer_B Operation13-11Timer_B13.2.4 Capture/Compare BlocksThree or seven identical capture/compare blocks, TBCCRx, are present inTimer_B. Any of the b

Timer_B Operation13-12 Timer_BFigure 13−11.Capture CycleSecondCaptureTakenCOV = 1CaptureTakenNoCaptureTakenReadTakenCaptureClear Bit COVin Register TB

Timer_B Operation13-13Timer_BCompare Latch TBCLxThe TBCCRx compare latch, TBCLx, holds the data for the comparison to thetimer value in compare mode.

Timer_B Operation13-14 Timer_B13.2.5 Output UnitEach capture/compare block contains an output unit. The output unit is usedto generate output signals

Timer_B Operation13-15Timer_BOutput Example—Timer in Up ModeThe OUTx signal is changed when the timer counts up to the TBCLx value, androlls from TBCL

Timer_B Operation13-16 Timer_BOutput Example—Timer in Continuous ModeThe OUTx signal is changed when the timer reaches the TBCLx and TBCL0values, depe

Timer_B Operation13-17Timer_BOutput Example − Timer in Up/Down ModeThe OUTx signal changes when the timer equals TBCLx in either countdirection and wh

System Reset and Initialization2-7System Resets, Interrupts, and Operating ModesFigure 2−4. Block Diagram of (Non)-Maskable Interrupt SourcesFlash Mod

Timer_B Operation13-18 Timer_B13.2.6 Timer_B InterruptsTwo interrupt vectors are associated with the 16-bit Timer_B module:- TBCCR0 interrupt vector f

Timer_B Operation13-19Timer_BTBIV, Interrupt Handler ExamplesThe following software example shows the recommended use of TBIV and thehandling overhead

Timer_B Registers13-20 Timer_B13.3 Timer_B RegistersThe Timer_B registers are listed in Table 13−5.Table 13−5.Timer_B RegistersRegister Short Form Reg

Timer_B Registers13-21Timer_BTimer_B Control Register TBCTL15 14 13 12 11 10 9 8UnusedTBCLGRPx CNTLx Unused TBSSELxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

Timer_B Registers13-22 Timer_BUnusedBit 3 UnusedTBCLRBit 2 Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the countdirection. The

Timer_B Registers13-23Timer_BTBCCTLx, Capture/Compare Control Register15 14 13 12 11 10 9 8CMxCCISx SCS CLLDx CAPrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw

Timer_B Registers13-24 Timer_BCCIEBit 4 Capture/compare interrupt enable. This bit enables the interrupt request ofthe corresponding CCIFG flag.0 Inte

Timer_B Registers13-25Timer_BTBIV, Timer_B Interrupt Vector Register15 14 13 12 11 10 9 800 0 0 0 0 0 0r0 r0 r0 r0 r0 r0 r0 r0765432100 0 0 0 TBIVx 0r

14-1USART Peripheral Interface, UART Mode    The universal synchronous/asynchronous receive/transmit (USART)perip

USART Introduction: UART Mode14-2 USART Peripheral Interface, UART Mode14.1 USART Introduction: UART ModeIn asynchronous mode, the USART connects the

System Reset and Initialization2-8 System Resets, Interrupts, and Operating ModesOscillator FaultThe oscillator fault signal warns of a possible error

USART Introduction: UART Mode14-3USART Peripheral Interface, UART ModeFigure 14−1. USART Block Diagram: UART ModeReceiver Shift RegisterTransmit Shift

USART Operation: UART Mode14-4 USART Peripheral Interface, UART Mode14.2 USART Operation: UART ModeIn UART mode, the USART transmits and receives char

USART Operation: UART Mode14-5USART Peripheral Interface, UART Mode14.2.3 Asynchronous Communication FormatsWhen two devices communicate asynchronousl

USART Operation: UART Mode14-6 USART Peripheral Interface, UART ModeThe URXWIE bit is used to control data reception in the idle-linemultiprocessor fo

USART Operation: UART Mode14-7USART Peripheral Interface, UART ModeAddress-Bit Multiprocessor FormatWhen MM = 1, the address-bit multiprocessor format

USART Operation: UART Mode14-8 USART Peripheral Interface, UART ModeAutomatic Error DetectionGlitch suppression prevents the USART from being accident

USART Operation: UART Mode14-9USART Peripheral Interface, UART Mode14.2.4 USART Receive EnableThe receive enable bit, URXEx, enables or disables data

USART Operation: UART Mode14-10 USART Peripheral Interface, UART Mode14.2.5 USART Transmit EnableWhen UTXEx is set, the UART transmitter is enabled. T

USART Operation: UART Mode14-11USART Peripheral Interface, UART Mode14.2.6 UART Baud Rate GenerationThe USART baud rate generator is capable of produc

USART Operation: UART Mode14-12 USART Peripheral Interface, UART ModeBaud Rate Bit TimingThe first stage of the baud rate generator is the 16-bit coun

System Reset and Initialization2-9System Resets, Interrupts, and Operating ModesExample of an NMI Interrupt HandlerThe NMI interrupt is a multiple-sou

USART Operation: UART Mode14-13USART Peripheral Interface, UART ModeTransmit Bit TimingThe timing for each character is the sum of the individual bit

USART Operation: UART Mode14-14 USART Peripheral Interface, UART ModeReceive Bit TimingReceive timing consists of two error sources. The first is the

USART Operation: UART Mode14-15USART Peripheral Interface, UART ModeFor example, the receive errors for the following conditions are calculated:Baud r

USART Operation: UART Mode14-16 USART Peripheral Interface, UART ModeTypical Baud Rates and ErrorsStandard baud rate frequency data for UxBRx and UxMC

USART Operation: UART Mode14-17USART Peripheral Interface, UART Mode14.2.7 USART InterruptsThe USART has one interrupt vector for transmission and one

USART Operation: UART Mode14-18 USART Peripheral Interface, UART ModeUSART Receive Interrupt OperationThe URXIFGx interrupt flag is set each time a ch

USART Operation: UART Mode14-19USART Peripheral Interface, UART ModeReceive-Start Edge Detect OperationThe URXSE bit enables the receive start-edge de

USART Operation: UART Mode14-20 USART Peripheral Interface, UART ModeReceive-Start Edge Detect ConditionsWhen URXSE = 1, glitch suppression prevents t

USART Registers: UART Mode14-21USART Peripheral Interface, UART Mode14.3 USART Registers: UART ModeTable 14−3 lists the registers for all devices impl

USART Registers: UART Mode14-22 USART Peripheral Interface, UART ModeUxCTL, USART Control Register76543210PENA PEV SPB CHAR LISTEN SYNC MM SWRSTrw−0 r

System Reset and Initialization2-10 System Resets, Interrupts, and Operating ModesEach individual peripheral interrupt is discussed in the associated

USART Registers: UART Mode14-23USART Peripheral Interface, UART ModeUxTCTL, USART Transmit Control Register76543210Unused CKPL SSELx URXSE TXWAKE Unus

USART Registers: UART Mode14-24 USART Peripheral Interface, UART ModeUxRCTL, USART Receive Control Register76543210FE PE OE BRK URXEIE URXWIE RXWAKE R

USART Registers: UART Mode14-25USART Peripheral Interface, UART ModeUxBR0, USART Baud Rate Control Register 0765432102726252423222120rw rw rw rw rw rw

USART Registers: UART Mode14-26 USART Peripheral Interface, UART ModeUxRXBUF, USART Receive Buffer Register765432102726252423222120r r r r r r r rUxRX

USART Registers: UART Mode14-27USART Peripheral Interface, UART ModeME1, Module Enable Register 176543210UTXE0 URXE0rw−0 rw−0UTXE0Bit 7 USART0 transmi

USART Registers: UART Mode14-28 USART Peripheral Interface, UART ModeIE1, Interrupt Enable Register 176543210UTXIE0 URXIE0rw−0 rw−0UTXIE0Bit 7 USART0

USART Registers: UART Mode14-29USART Peripheral Interface, UART ModeIFG1, Interrupt Flag Register 176543210UTXIFG0 URXIFG0rw−1 rw−0UTXIFG0†Bit 7 USART

15-1USART Peripheral Interface, SPI Mode USART Peripheral Interface, SPI ModeThe universal synchronous/asynchronous receive/transmit (USART)peripheral

USART Introduction: SPI Mode15-2 USART Peripheral Interface, SPI Mode15.1 USART Introduction: SPI ModeIn synchronous mode, the USART connects the MSP4

USART Introduction: SPI Mode15-3USART Peripheral Interface, SPI ModeFigure 15−1. USART Block Diagram: SPI ModeReceiver Shift RegisterTransmit Shift Re

System Reset and Initialization2-11System Resets, Interrupts, and Operating ModesReturn From InterruptThe interrupt handling routine terminates with t

USART Operation: SPI Mode15-4 USART Peripheral Interface, SPI Mode15.2 USART Operation: SPI ModeIn SPI mode, serial data is transmitted and received b

USART Operation: SPI Mode15-5USART Peripheral Interface, SPI Mode15.2.2 Master ModeFigure 15−2. USART Master and External SlaveReceive Buffer UxRXBUFR

USART Operation: SPI Mode15-6 USART Peripheral Interface, SPI Mode15.2.3 Slave ModeFigure 15−3. USART Slave and External MasterReceive Buffer UxRXBUFR

USART Operation: SPI Mode15-7USART Peripheral Interface, SPI Mode15.2.4 SPI EnableThe SPI transmit/receive enable bit USPIEx enables or disables the U

USART Operation: SPI Mode15-8 USART Peripheral Interface, SPI ModeReceive EnableThe SPI receive enable state diagrams are shown in Figure 15−6 andFigu

USART Operation: SPI Mode15-9USART Peripheral Interface, SPI Mode15.2.5 Serial Clock ControlUCLK is provided by the master on the SPI bus. When MM = 1

USART Operation: SPI Mode15-10 USART Peripheral Interface, SPI ModeSerial Clock Polarity and PhaseThe polarity and phase of UCLK are independently con

USART Operation: SPI Mode15-11USART Peripheral Interface, SPI Mode15.2.6 SPI InterruptsThe USART has one interrupt vector for transmission and one int

USART Operation: SPI Mode15-12 USART Peripheral Interface, SPI ModeSPI Receive Interrupt OperationThe URXIFGx interrupt flag is set each time a charac

USART Registers: SPI Mode15-13USART Peripheral Interface, SPI Mode15.3 USART Registers: SPI ModeTable 15−1 lists the registers for all devices impleme

Related Documentation From Texas Instrumentsiii PrefaceRead This FirstAbout This ManualThis manual discusses modules and peripherals of the MSP430x4x

System Reset and Initialization2-12 System Resets, Interrupts, and Operating Modes2.2.4 Interrupt VectorsThe interrupt vectors and the power-up starti

USART Registers: SPI Mode15-14 USART Peripheral Interface, SPI ModeUxCTL, USART Control Register76543210Unused Unused I2C†CHAR LISTEN SYNC MM SWRSTrw−

USART Registers: SPI Mode15-15USART Peripheral Interface, SPI ModeUxTCTL, USART Transmit Control Register76543210CKPH CKPL SSELx Unused Unused STC TXE

USART Registers: SPI Mode15-16 USART Peripheral Interface, SPI ModeUxRCTL, USART Receive Control Register76543210FE Unused OE Unused Unused Unused Unu

USART Registers: SPI Mode15-17USART Peripheral Interface, SPI ModeUxBR0, USART Baud Rate Control Register 0765432102726252423222120rw rw rw rw rw rw r

USART Registers: SPI Mode15-18 USART Peripheral Interface, SPI ModeUxRXBUF, USART Receive Buffer Register765432102726252423222120r r r r r r r rUxRXBU

USART Registers: SPI Mode15-19USART Peripheral Interface, SPI ModeME1, Module Enable Register 176543210USPIE0rw−0Bit 7 This bit may be used by other m

USART Registers: SPI Mode15-20 USART Peripheral Interface, SPI ModeIE1, Interrupt Enable Register 176543210UTXIE0 URXIE0rw−0 rw−0UTXIE0Bit 7 USART0 tr

USART Registers: SPI Mode15-21USART Peripheral Interface, SPI ModeIFG1, Interrupt Flag Register 176543210UTXIFG0 URXIFG0rw−1 rw−0UTXIFG0Bit 7 USART0 t

16-1OA OAThe OA is a general purpose operational amplifier. This chapter describes theOA. Three OA modules are implemented in the MSP430FG43x devices.

OA Introduction16-2 OA16.1 OA IntroductionThe OA op amps support front-end analog signal conditioning prior to analog-to-digital conversion.Features o

Operating Modes2-13System Resets, Interrupts, and Operating Modes2.3 Operating ModesThe MSP430 family is designed for ultralow-power applications and

OA Introduction16-3OAFigure 16−1. OA Block DiagramOAPMxOAPx011OAFBRxA12 ext. (OA0)A13 ext. (OA1)A14 ext. (OA2)OAADC04R4R2R2RRRRROAxOUTRBOTTOMRTOPOAx+−

OA16-4 OA16.2 OA OperationThe OA module is configured with user software. The setup and operation ofthe OA is discussed in the following sections.16.2

OA16-5OA16.2.4 OA ConfigurationsThe OA can be configured for different amplifier functions with the OAFCx bits.as listed in Table 16−1.Table 16−1.OA M

OA16-6 OANon-Inverting PGA ModeIn this mode the output of the OAx is connected to RTOP and RBOTTOM isconnected to AVSS. The OAxTAP signal is connected

OA16-7OAFigure 16−2 shows an example of a two-opamp differential amplifier usingOA0 and OA1. The control register settings and are shown in Table 16−2

OA16-8 OAFigure 16−3. Two Opamp Differential Amplifier OAx InterconnectionsOAPx00011011OAPMx011OAFBRxA13 ext.OAADC04R4R2R2RRRRROA1+−OAADC1010001101100

OA16-9OAFigure 16−4 shows an example of a three-opamp differential amplifier usingOA0, OA1 and OA2. The control register settings are shown in Table 1

OA16-10 OAFigure 16−5. Three Opamp Differential Amplifier OAx InterconnectionsOAPMxOAPxOAFBRx4R4R2R2RRRRROA0OUTOA0RBOTTOMOA0+−OA0TAP000110110100011011

OA Registers16-11OA16.3 OA RegistersThe OA registers are listed in Table 16−6.Table 16−6.Register Short Form Register Type Address Initial StateOA0 Co

OA Registers16-12 OAOAxCTL0, Opamp Control Register 076543210OANx OAPx OAPMx OAADC1 OAADC0rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0OANxBits7-6Inverting

Operating Modes2-14 System Resets, Interrupts, and Operating ModesFigure 2−9. MSP430x4xx Operating Modes For Basic Clock SystemActive ModeCPU Is Activ

OA Registers16-13OAOAxCTL1, Opamp Control Register 176543210OAFBRx OAFCx Reserved OARRIPrw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0OAFBRxBits7-5OAx feedba

17-1Comparator_A Comparator_AComparator_A is an analog voltage comparator. This chapter describesComparator_A. Comparator_A is implemented in all MSP4

Comparator_A Introduction17-2 Comparator_A17.1 Comparator_A IntroductionThe comparator_A module supports precision slope analog-to-digitalconversions,

Comparator_A Introduction17-3Comparator_AFigure 17−1. Comparator_A Block DiagramCAOUT+−CAEX0.5x0.25xSet_CAIFGCA1CCI1B+−0VGDSP2CA0P2CA1CAFCARSELCAONCAR

Comparator_A Operation17-4 Comparator_A17.2 Comparator_A Operation The comparator_A module is configured with user software. The setup andoperation of

Comparator_A Operation17-5Comparator_A17.2.3 Output FilterThe output of the comparator can be used with or without internal filtering.When control bit

Comparator_A Operation17-6 Comparator_A17.2.5 Comparator_A, Port Disable Register CAPDThe comparator input and output functions are multiplexed with t

Comparator_A Operation17-7Comparator_A17.2.7 Comparator_A Used to Measure Resistive ElementsThe Comparator_A can be optimized to precisely measure res

Comparator_A Operation17-8 Comparator_AThe thermistor measurement is based on a ratiometric conversion principle.The ratio of two capacitor discharge

Comparator_A Registers17-9Comparator_A17.3 Comparator_A RegistersThe Comparator_A registers are listed in Table 17−1.Table 17−1.Comparator_A Registers

Operating Modes2-15System Resets, Interrupts, and Operating Modes2.3.1 Entering and Exiting Low-Power ModesAn enabled interrupt event wakes the MSP430

Comparator_A Registers17-10 Comparator_ACACTL1, Comparator_A Control Register 176543210CAEX CARSEL CAREFx CAON CAIES CAIE CAIFGrw−(0) rw−(0) rw−(0) rw

Comparator_A Registers17-11Comparator_ACACTL2, Comparator_A Control Register 276543210Unused P2CA1 P2CA0 CAF CAOUTrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r

18-1LCD Controller LCD ControllerThe LCD controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapterdescribes LCD controller. The LCD controll

LCD Controller Introduction18-2 LCD Controller18.1 LCD Controller IntroductionThe LCD controller directly drives LCD displays by creating the ac segme

LCD Controller Introduction18-3LCD ControllerFigure 18−1. LCD Controller Block DiagramDisplayMemory20x8−bitsSegmentOutputControlMuxAnalogVoltageMultip

LCD Controller Operation18-4 LCD Controller18.2 LCD Controller OperationThe LCD controller is configured with user software. The setup and operationof

LCD Controller Operation18-5LCD Controller18.2.4 LCD Voltage GenerationThe voltages required for the LCD signals are supplied externally to pins R33,R

LCD Controller Operation18-6 LCD Controller18.2.6 Static ModeIn static mode, each MSP430 segment pin drives one LCD segment and onecommon line, COM0,

LCD Controller Operation18-7LCD ControllerFigure 18−4 shows an example static LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mappin

LCD Controller Operation18-8 LCD ControllerStatic Mode Software Example; All eight segments of a digit are often located in four; display memory bytes

Principles for Low-Power Applications2-16 System Resets, Interrupts, and Operating Modes2.4 Principles for Low-Power ApplicationsOften, the most impor

LCD Controller Operation18-9LCD Controller18.2.7 2-Mux ModeIn 2-mux mode, each MSP430 segment pin drives two LCD segments and twocommon lines, COM0 an

LCD Controller Operation18-10 LCD ControllerFigure 18−6 shows an example 2-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mappi

LCD Controller Operation18-11LCD Controller2-Mux Mode Software Example; All eight segments of a digit are often located in two; display memory bytes w

LCD Controller Operation18-12 LCD Controller18.2.8 3-Mux ModeIn 3-mux mode, each MSP430 segment pin drives three LCD segments andthree common lines, C

LCD Controller Operation18-13LCD ControllerFigure 18−8 shows an example 3-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mappin

LCD Controller Operation18-14 LCD Controller3-Mux Mode Software Example; The 3mux rate can support nine segments for each; digit. The nine segments of

LCD Controller Operation18-15LCD Controller18.2.9 4-Mux ModeIn 4-mux mode, each MSP430 segment pin drives four LCD segments and allfour common lines,

LCD Controller Operation18-16 LCD ControllerFigure 18−10 shows an example 4-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mapp

LCD Controller Operation18-17LCD Controller4-Mux Mode Software Example; The 4mux rate supports eight segments for each digit.; All eight segments of a

LCD Controller Operation18-18 LCD Controller18.3 LCD Controller RegistersThe LCD Controller registers are listed in Table 18−2.Table 18−2.LCD Controll

3-1RISC 16-Bit CPU   This chapter describes the MSP430 CPU, addressing modes, and instructionset.Topic Page3.1 CPU Introduction 3-2. .

LCD Controller Operation18-19LCD ControllerLCDCTL, LCD Control Register76543210LCDPx LCDMXx LCDSON Unused LCDONrw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0

19-1LCD_A Controller LCD_A ControllerThe LCD_A controller drives static, 2-mux, 3-mux, or 4-mux LCDs. Thischapter describes the LCD_A controller. The

LCD_A Controller Introduction19-2 LCD_A Controller19.1 LCD_A Controller IntroductionThe LCD_A controller directly drives LCD displays by creating the

LCD_A Controller Introduction19-3LCD_A ControllerFigure 19−1. LCD_A Controller Block DiagramVLCDREFxDisplayMemory20x8−bitsSegmentOutputControlMuxAnalo

LCD_A Controller Operation19-4 LCD_A Controller19.2 LCD_A Controller OperationThe LCD_A controller is configured with user software. The setup andoper

LCD_A Controller Operation19-5LCD_A Controller19.2.3 LCD_A Voltage And Bias GenerationThe LCD_A module allows selectable sources for the peak output w

LCD_A Controller Operation19-6 LCD_A ControllerTo source the bias voltages V2 − V4 externally, REXT is set. This also disablesthe internal bias genera

LCD_A Controller Operation19-7LCD_A ControllerThe internal bias generator supports 1/2 bias LCDs when LCD2B = 1, and 1/3bias LCDs when LCD2B = 0 in 2-

LCD_A Controller Operation19-8 LCD_A Controller19.2.4 LCD Timing GenerationThe LCD_A controller uses the fLCD signal from the integrated ACLK prescale

LCD_A Controller Operation19-9LCD_A Controller19.2.6 Static ModeIn static mode, each MSP430 segment pin drives one LCD segment and onecommon line, COM

CPU Introduction3-2 RISC 16-Bit CPU3.1 CPU Introduction The CPU incorporates features specifically designed for modernprogramming techniques such as c

LCD_A Controller Operation19-10 LCD_A ControllerFigure 19−5 shows an example static LCD, pin-out, LCD-to-MSP430connections, and the resulting segment

LCD_A Controller Operation19-11LCD_A ControllerStatic Mode Software Example; All eight segments of a digit are often located in four; display memory b

LCD_A Controller Operation19-12 LCD_A Controller19.2.7 2-Mux ModeIn 2-mux mode, each MSP430 segment pin drives two LCD segments and twocommon lines, C

LCD_A Controller Operation19-13LCD_A ControllerFigure 19−7 shows an example 2-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment ma

LCD_A Controller Operation19-14 LCD_A Controller2-Mux Mode Software Example; All eight segments of a digit are often located in two; display memory by

LCD_A Controller Operation19-15LCD_A Controller19.2.8 3-Mux ModeIn 3-mux mode, each MSP430 segment pin drives three LCD segments andthree common lines

LCD_A Controller Operation19-16 LCD_A ControllerFigure 19−9 shows an example 3-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment m

LCD_A Controller Operation19-17LCD_A Controller3-Mux Mode Software Example; The 3mux rate can support nine segments for each; digit. The nine segments

LCD_A Controller Operation19-18 LCD_A Controller19.2.9 4-Mux ModeIn 3-mux mode, each MSP430 segment pin drives four LCD segments and allfour common li

LCD_A Controller Operation19-19LCD_A ControllerFigure 19−11 shows an example 4-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment m

CPU Introduction3-3RISC 16-Bit CPUFigure 3−1. CPU Block Diagram015MDB − Memory Data Bus Memory Address Bus −MAB16Zero, ZCarry, COverflow, VNegative, N

LCD_A Controller Operation19-20 LCD_A Controller4-Mux Mode Software Example; The 4mux rate supports eight segments for each digit.; All eight segments

LCD_A Controller Operation19-21LCD_A Controller19.3 LCD Controller RegistersThe LCD Controller registers are listed in Table 19−2.Table 19−2.LCD Contr

LCD_A Controller Operation19-22 LCD_A ControllerLCDACTL, LCD_A Control Register76543210LCDFREQx LCDMXx LCDSON Unused LCDONrw−0 rw−0 rw−0 rw−0 rw−0 rw−

LCD_A Controller Operation19-23LCD_A ControllerLCDAPCTL0, LCD_A Port Control Register 076543210LCDS28 LCDS24 LCDS20 LCDS16 LCDS12 LCDS8 LCDS4 LCDS0rw−

LCD_A Controller Operation19-24 LCD_A ControllerLCDAPCTL1, LCD_A Port Control Register 176543210Unused LCDS36 LCDS32rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0

LCD_A Controller Operation19-25LCD_A ControllerLCDAVCTL0, LCD_A Voltage Control Register 076543210Unused R03EXT REXT VLCDEXT LCDCPEN VLCDREFx LCD2Brw−

LCD_A Controller Operation19-26 LCD_A ControllerLCDAVCTL1, LCD_A Voltage Control Register 176543210Unused VLCDx Unusedrw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw

20-1ADC12 ADC12The ADC12 module is a high-performance 12-bit analog-to-digital converter.This chapter describes the ADC12. The ADC12 is implemented in

ADC12 Introduction20-2 ADC1220.1 ADC12 IntroductionThe ADC12 module supports fast, 12-bit analog-to-digital conversions. Themodule implements a 12-bit

ADC12 Introduction20-3ADC12Figure 20−1. ADC12 Block DiagramSampleandHoldVeREF+12−bit SARVR−−16 x 12MemoryBuffer−−16 x 8MemoryControl−VR+VREF+VeREF−VRE

CPU Registers3-4 RISC 16-Bit CPU3.2 CPU RegistersThe CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 havededicated functions. R4 to R15 a

ADC12 Operation20-4 ADC1220.2 ADC12 OperationThe ADC12 module is configured with user software. The setup and operationof the ADC12 is discussed in th

ADC12 Operation20-5ADC1220.2.2 ADC12 Inputs and MultiplexerThe eight external and four internal analog signals are selected as the channelfor conversi

ADC12 Operation20-6 ADC1220.2.3 Voltage Reference GeneratorThe ADC12 module contains a built-in voltage reference with two selectablevoltage levels, 1

ADC12 Operation20-7ADC1220.2.5 Sample and Conversion TimingAn analog-to-digital conversion is initiated with a rising edge of the sampleinput signal S

ADC12 Operation20-8 ADC12Pulse Sample ModeThe pulse sample mode is selected when SHP = 1. The SHI signal is used totrigger the sampling timer. The SHT

ADC12 Operation20-9ADC12Sample Timing ConsiderationsWhen SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON =1, the selected Ax input can be m

ADC12 Operation20-10 ADC1220.2.6 Conversion MemoryThere are 16 ADC12MEMx conversion memory registers to store conversionresults. Each ADC12MEMx is con

ADC12 Operation20-11ADC12Single-Channel Single-Conversion ModeA single channel is sampled and converted once. The ADC result is written tothe ADC12MEM

ADC12 Operation20-12 ADC12Sequence-of-Channels ModeA sequence of channels is sampled and converted once. The ADC results arewritten to the conversion

ADC12 Operation20-13ADC12Repeat-Single-Channel ModeA single channel is sampled and converted continuously. The ADC results arewritten to the ADC12MEMx

CPU Registers3-5RISC 16-Bit CPU3.2.2 Stack Pointer (SP)The stack pointer (SP/R1) is used by the CPU to store the return addressesof subroutine calls a

ADC12 Operation20-14 ADC12Repeat-Sequence-of-Channels ModeA sequence of channels is sampled and converted repeatedly. The ADCresults are written to th

ADC12 Operation20-15ADC12Using the Multiple Sample and Convert (MSC) BitTo configure the converter to perform successive conversions automaticallyand

ADC12 Operation20-16 ADC1220.2.8 Using the Integrated Temperature SensorTo use the on-chip temperature sensor, the user selects the analog inputchanne

ADC12 Operation20-17ADC1220.2.9 ADC12 Grounding and Noise ConsiderationsAs with any high-resolution ADC, appropriate printed-circuit-board layout andg

ADC12 Operation20-18 ADC1220.2.10 ADC12 InterruptsThe ADC12 has 18 interrupt sources:- ADC12IFG0-ADC12IFG15- ADC12OV, ADC12MEMx overflow- ADC12TOV, AD

ADC12 Operation20-19ADC12ADC12 Interrupt Handling Software ExampleThe following software example shows the recommended use of ADC12IVand the handling

ADC12 Registers20-20 ADC1220.3 ADC12 RegistersThe ADC12 registers are listed in Table 20−2 .Table 20−2.ADC12 RegistersRegister Short Form Register Typ

ADC12 Registers20-21ADC12ADC12CTL0, ADC12 Control Register 015 14 13 12 11 10 9 8SHT1x SHT0xrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)765

ADC12 Registers20-22 ADC12MSCBit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.0 The sampling timer requires a rising ed

ADC12 Registers20-23ADC12ADC12CTL1, ADC12 Control Register 115 14 13 12 11 10 9 8CSTARTADDx SHSx SHP ISSHrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−

GlossaryivGlossaryACLK Auxiliary Clock See Basic Clock ModuleADC Analog-to-Digital ConverterBOR Brown-Out Reset See System Resets, Interrupts, and Ope

CPU Registers3-6 RISC 16-Bit CPU3.2.3 Status Register (SR)The status register (SR/R2), used as a source or destination register, can beused in the reg

ADC12 Registers20-24 ADC12ADC12SSELxBits4-3ADC12 clock source select00 ADC12OSC01 ACLK10 MCLK11 SMCLKCONSEQxBits2-1Conversion sequence mode select00 S

ADC12 Registers20-25ADC12ADC12MCTLx, ADC12 Conversion Memory Control Registers76543210EOS SREFx INCHxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

ADC12 Registers20-26 ADC12ADC12IE, ADC12 Interrupt Enable Register15 14 13 12 11 10 9 8ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC

ADC12 Registers20-27ADC12ADC12IV, ADC12 Interrupt Vector Register15 14 13 12 11 10 9 800 0 0 0 0 0 0r0 r0 r0 r0 r0 r0 r0 r0765432100 0 ADC12IVx 0r0 r0

21-1SD16 SD16The SD16 module is a multichannel 16-bit, sigma-delta analog-to-digitalconverter. This chapter describes the SD16. The SD16 module isimpl

SD16 Introduction21-2 SD1621.1 SD16 IntroductionThe SD16 module consists of up to three independent sigma-deltaanalog-to-digital converters and an int

SD16 Introduction21-3SD16Figure 21−1. SD16 Block DiagramChannel 0Channel 115 0SD16 Control BlockSD16DIVxfMACLKTACLKSD16SSELx0001101100011011MCLKSMCLKA

SD16 Operation21-4 SD1621.2 SD16 OperationThe SD16 module is configured with user software. The setup and operationof the SD16 is discussed in the fol

SD16 Operation21-5SD1621.2.5 Channel SelectionEach SD16 channel can convert up to 8 differential pair inputs multiplexed intothe PGA. Up to six input

SD16 Operation21-6 SD1621.2.6 Digital FilterThe digital filter processes the 1-bit data stream from the modulator using aSINC3 comb filter. The transf

CPU Registers3-7RISC 16-Bit CPU3.2.4 Constant Generator Registers CG1 and CG2Six commonly-used constants are generated with the constant generatorregi

SD16 Operation21-7SD16Figure 21−3 shows the digital filter step response and conversion points. Forstep changes at the input after start of conversion

SD16 Operation21-8 SD16Digital Filter OutputThe number of bits output by each digital filter is dependent on theoversampling ratio and ranges from 16

SD16 Operation21-9SD1621.2.7 Conversion Memory Registers: SD16MEMxOne SD16MEMx register is associated with each SD16 channel. Conversionresults for ea

SD16 Operation21-10 SD1621.2.8 Conversion ModesThe SD16 module can be configured for four modes of operation, listed inTable 21−2. The SD16SNGL and SD

SD16 Operation21-11SD16Figure 21−6. Single Channel OperationChannel 0SD16SNGL = 1SD16GRP = 0TimeConversionSD16SCChannel 1SD16SNGL = 1SD16GRP = 0Conver

SD16 Operation21-12 SD16Group of Channels, Continuous ConversionWhen SD16SNGL = 0 for a channel in a group, continuous conversion modeis selected. Con

SD16 Operation21-13SD1621.2.9 Conversion Operation Using PreloadWhen multiple channels are grouped the SD16PREx registers can be used todelay the conv

SD16 Operation21-14 SD16Figure 21−9. Start of Conversion using PreloadDelayed Conversion40SD16OSRx = 32Start ofConversionTimeConversion32Conversion32f

SD16 Operation21-15SD1621.2.10 Using the Integrated Temperature SensorTo use the on-chip temperature sensor, the user selects the analog inputchannel

SD16 Operation21-16 SD1621.2.11 Interrupt HandlingThe SD16 has 2 interrupt sources for each ADC channel:- SD16IFG- SD16OVIFGThe SD16IFG bits are set w

CPU Registers3-8 RISC 16-Bit CPU3.2.5 General−Purpose Registers R4 - R15The twelve registers, R4−R15, are general-purpose registers. All of theseregis

SD16 Operation21-17SD16SD16 Interrupt Handling Software ExampleThe following software example shows the recommended use of SD16IV andthe handling over

SD16 Registers21-18 SD1621.3 SD16 RegistersThe SD16 registers are listed in Table 21−3:Table 21−3.SD16 RegistersRegister Short Form Register Type Addr

SD16 Registers21-19SD16SD16CTL, SD16 Control Register15 14 13 12 11 10 9 8Reserved SD16LPr0 r0 r0 r0 r0 r0 r0 rw−076543210SD16DIVx SD16SSELxSD16VMIDON

SD16 Registers21-20 SD16SD16CCTLx, SD16 Channel x Control Register15 14 13 12 11 10 9 8Reserved SD16SNGL SD16OSRxr0 r0 r0 r0 r0 rw−0 rw−0 rw−076543210

SD16 Registers21-21SD16SD16IFGBit 2 SD16 interrupt flag. SD16IFG is set when new conversion results areavailable. SD16IFG is automatically reset when

SD16 Registers21-22 SD16SD16MEMx, SD16 Channel x Conversion Memory Register15 14 13 12 11 10 9 8Conversion Resultsr r r r r r r r76543210Conversion Re

SD16 Registers21-23SD16SD16IV, SD16 Interrupt Vector Register15 14 13 12 11 10 9 800 0 0 0 0 0 0r0 r0 r0 r0 r0 r0 r0 r0765432100 0 0 SD16IVx 0r0 r0 r0

22-1SD16_A SD16_AThe SD16_A module is a single-converter 16-bit, sigma-delta analog-to-digitalconversion module with high impedance input buffer. This

SD16_A Introduction22-2 SD16_A22.1 SD16_A IntroductionThe SD16_A module consists of one sigma-delta analog-to-digital converterwith an high impedance

SD16_A Introduction22-3SD16_AFigure 22−1. SD16_A Block Diagram15 0SD16DIVxACLKTACLKSD16SSELx0001101100011011MCLKSMCLKAVCCVREFDivider1/2/4/8A0000SD16IN

Addressing Modes3-9RISC 16-Bit CPU3.3 Addressing ModesSeven addressing modes for the source operand and four addressing modesfor the destination opera

SD16_A Operation22-4 SD16_A22.2 SD16_A OperationThe SD16_A module is configured with user software. The setup andoperation of the SD16_A is discussed

SD16_A Operation22-5SD16_A22.2.5 Channel SelectionThe SD16_A can convert up to 8 differential pair inputs multiplexed into thePGA. Up to five input pa

SD16_A Operation22-6 SD16_A22.2.7 Digital FilterThe digital filter processes the 1-bit data stream from the modulator using aSINC3 comb filter. The tr

SD16_A Operation22-7SD16_AFigure 22−3 shows the digital filter step response and conversion points. Forstep changes at the input after start of conver

SD16_A Operation22-8 SD16_ADigital Filter OutputThe number of bits output by the digital filter is dependent on the oversamplingratio and ranges from

SD16_A Operation22-9SD16_A04812162024153269723 22 21 19 18 17 15 14 13 11 1028 27 26 252904812162024153269723 22 21 19 18 17 15 14 13 11 1028 27 26 25

SD16_A Operation22-10 SD16_A22.2.8 Conversion Memory Register: SD16MEM0The SD16MEM0 register is associated with the SD16_A channel. Conversionresults

SD16_A Operation22-11SD16_A22.2.9 Conversion ModesThe SD16_A module can be configured for two modes of operation, listed inTable 22−3. The SD16SNGL bi

SD16_A Operation22-12 SD16_A22.2.10 Using the Integrated Temperature SensorTo use the on-chip temperature sensor, the user selects the analog inputcha

SD16_A Operation22-13SD16_A22.2.11 Interrupt HandlingThe SD16_A has 2 interrupt sources for its ADC channel:- SD16IFG- SD16OVIFGThe SD16IFG bit is set

Addressing Modes3-10 RISC 16-Bit CPU3.3.1 Register ModeThe register mode is described in Table 3−4.Table 3−4.Register Mode DescriptionAssembler Code C

SD16_A Registers22-14 SD16_A22.3 SD16_A RegistersThe SD16_A registers are listed in Table 22−4:Table 22−4.SD16_A RegistersRegister Short Form Register

SD16_A Registers22-15SD16_ASD16CTL, SD16_A Control Register15 14 13 12 11 10 9 8Reserved SD16XDIV SD16LPr0 r0 r0 r0 rw−0 rw−0 rw−0 rw−076543210SD16DIV

SD16_A Registers22-16 SD16_ASD16CCTL0, SD16_A Control Register 015 14 13 12 11 10 9 8Reserved SD16BUFx SD16UNI SD16XOSR SD16SNGL SD16OSRxr0 rw−0 rw−0

SD16_A Registers22-17SD16_ASD16LSBACCBit 6 LSB access. This bit allows access to the upper or lower 16-bits of theSD16_A conversion result.0 SD16MEMx

SD16_A Registers22-18 SD16_ASD16INCTL0, SD16_A Input Control Register76543210SD16INTDLYx SD16GAINx SD16INCHxrw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0SD1

SD16_A Registers22-19SD16_ASD16MEM0, SD16_A Conversion Memory Register15 14 13 12 11 10 9 8Conversion Resultsr r r r r r r r76543210Conversion Results

SD16_A Registers22-20 SD16_ASD16IV, SD16_A Interrupt Vector Register15 14 13 12 11 10 9 800 0 0 0 0 0 0r0 r0 r0 r0 r0 r0 r0 r0765432100 0 0 SD16IVx 0r

23-1DAC12 DAC12The DAC12 module is a 12-bit, voltage output digital-to-analog converter. Thischapter describes the DAC12. Two DAC12 modules are implem

DAC12 Introduction23-2 DAC1223.1 DAC12 IntroductionThe DAC12 module is a 12-bit, voltage output DAC. The DAC12 can beconfigured in 8- or 12-bit mode a

DAC12 Introduction23-3DAC12Figure 23−1. DAC12 Block DiagramDAC12_0DAC12_0OUT2.5V or 1.5V reference from ADC12DAC12SREFxVR−VR+DAC12_0DATDAC12_0LatchDAC

Addressing Modes3-11RISC 16-Bit CPU3.3.2 Indexed ModeThe indexed mode is described in Table 3−5.Table 3−5.Indexed Mode DescriptionAssembler Code Conte

DAC12 Introduction23-4 DAC12Figure 23−2. DAC12 Block Diagram For MSPx42x0 DevicesDAC12_0DAC12_0OUT1.2V reference from SD16DAC12SREFxVR−VR+DAC12_0DATDA

DAC12 Operation23-5DAC1223.2 DAC12 OperationThe DAC12 module is configured with user software. The setup and operationof the DAC12 is discussed in the

DAC12 Operation23-6 DAC1223.2.2 DAC12 ReferenceOn MSP430FG43x devices, the reference for the DAC12 is configured to useeither an external reference vo

DAC12 Operation23-7DAC1223.2.4 DAC12_xDAT Data FormatThe DAC12 supports both straight binary and 2’s compliment data formats.When using straight binar

DAC12 Operation23-8 DAC1223.2.5 DAC12 Output Amplifier Offset CalibrationThe offset voltage of the DAC12 output amplifier can be positive or negative.

DAC12 Operation23-9DAC1223.2.6 Grouping Multiple DAC12 ModulesMultiple DAC12s can be grouped together with the DAC12GRP bit tosynchronize the update o

DAC12 Operation23-10 DAC1223.2.7 DAC12 InterruptsThe DAC12 interrupt vector is shared with the DMA controller. Software mustcheck the DAC12IFG and DMA

DAC12 Registers23-11DAC1223.3 DAC12 RegistersThe DAC12 registers are listed in Table 23−2.Table 23−2.DAC12 RegistersRegister Short Form Register Type

DAC12 Registers23-12 DAC12DAC12_xCTL, DAC12 Control Register15 14 13 12 11 10 9 8DAC12OPS DAC12SREFx DAC12RES DAC12LSELxDAC12CALONDAC12IRrw−(0) rw−(0)

DAC12 Registers23-13DAC12DAC12CALONBit 9 DAC12 calibration on. This bit initiates the DAC12 offset calibration sequenceand is automatically reset when

Addressing Modes3-12 RISC 16-Bit CPU3.3.3 Symbolic ModeThe symbolic mode is described in Table 3−6.Table 3−6.Symbolic Mode DescriptionAssembler Code C

DAC12 Registers23-14 DAC12DAC12_xDAT, DAC12 Data Register15 14 13 12 11 10 9 80 0 0 0 DAC12 Datar(0) r(0) r(0) r(0) rw−(0) rw−(0) rw−(0) rw−(0)7654321

24-1Scan IF  The Scan IF peripheral automatically scans sensors and measures linear orrotational motion. This chapter describes the Scan interf

Scan IF Introduction24-2 Scan IF24.1 Scan IF IntroductionThe Scan IF module is used to automatically measure linear or rotationalmotion with the low

Scan IF Introduction24-3Scan IFFigure 24−1. Scan IF Block DiagramTiming StateMachine (TSM)w/ oscillatorProcessing StateMachine (PSM)Analog Input Mult

Scan IF Operation24-4 Scan IF24.2 Scan IF OperationThe Scan IF is configured with user software. The setup and operation of theScan IF is discussed

Scan IF Operation24-5Scan IFFigure 24−2. Scan IF Analog Front End Block DiagramSIFTESTDSIFTESTS1(tsm)+−10SIFCH0SIFCH1SIFCH200011011SIFCH310SIFCISIFCI

Scan IF Operation24-6 Scan IFExcitationThe excitation circuitry is used to excite the LC sensors or to power the resistordividers. The excitation cir

Scan IF Operation24-7Scan IFFigure 24−3. Excitation and Sample-And-Hold CircuitrySIFEX(tsm)SIFVSS1110SIFCH0SIFCOMSample-and-HoldSIFLCEN(tsm)SIFTEN10D

Scan IF Operation24-8 Scan IFSample-And-HoldThe sample-and-hold is used to sample the sensor voltage to be measured.The sample-and-hold circuitry is

Scan IF Operation24-9Scan IFDirect Analog And Digital InputsBy setting the SIFCAX bit, external analog or digital signals can be connecteddirectly to

Addressing Modes3-13RISC 16-Bit CPU3.3.4 Absolute ModeThe absolute mode is described in Table 3−7.Table 3−7.Absolute Mode DescriptionAssembler Code Co

Scan IF Operation24-10 Scan IFWhen SIFCAX = 1, the SIFCSEL and SIFCI3 bits select between the SIFCIxchannels and the SIFCI input allowing storage of

Scan IF Operation24-11Scan IFComparator and DACThe analog input signals are converted into digital signals by the comparatorand the programmable 10-b

Scan IF Operation24-12 Scan IFFor each input there are two DAC registers to set the reference level as listedin Table 24−3. Together with the last st

Scan IF Operation24-13Scan IFInternal Signal Connections to Timer1_A5The outputs of the analog front end are connected to 3 differentcapture/compare

Scan IF Operation24-14 Scan IF24.2.2 Scan IF Timing State MachineThe TSM is a sequential state machine that cycles through the SIFTSMxregisters and c

Scan IF Operation24-15Scan IFFigure 24−8. Timing State Machine Block DiagramSIFDIV3BxState PointerandControlStartStopSIFTSM0SIFTSM23Set_SIFIFG2SIFTSM

Scan IF Operation24-16 Scan IFTSM OperationThe TSM state machine automatically starts and re-starts periodically basedon a divided ACLK start signal

Scan IF Operation24-17Scan IFTSM State Clock Source SelectThe TSM clock source is individually configurable for each state. The TSM canbe clocked fro

Scan IF Operation24-18 Scan IFTSM Test CyclesFor calibration purposes, to detect sensor drift, or to measure signals otherthan the sensor signals, a

Scan IF Operation24-19Scan IFTSM ExampleFigure 24−10 shows an example for a TSM sequence. The TSMx registervalues for the example are shown in Table

Addressing Modes3-14 RISC 16-Bit CPU3.3.5 Indirect Register ModeThe indirect register mode is described in Table 3−8.Table 3−8.Indirect Mode Descripti

Scan IF Operation24-20 Scan IF24.2.3 Scan IF Processing State MachineThe PSM is a programmable state machine used to determine rotation anddirection

Scan IF Operation24-21Scan IFFigure 24−11.Scan IF Processing State Machine Block DiagramQ0Q3Q4Q5Q6Q7S2S1SIFQ6ENSIFQ7ENQ7 . . . Q0Q0Q1Q2Q3Q4Q5Q6Q7MSP

Scan IF Operation24-22 Scan IFThe current-state and next-state logic are reset while the Scan IF is disabled.One of the bytes stored at addresses SIF

Scan IF Operation24-23Scan IFPSM CountersThe PSM has two 8-bit counters SIFCNT1 and SIFCNT2. SIFCNT1 is updatedwith Q1 and Q2 and SIFCNT2 is updated

Scan IF Operation24-24 Scan IFSimplest State MachineFigure 24−12 shows the simplest state machine that can be realized with thePSM. The following cod

Scan IF Operation24-25Scan IFIf the PSM is in state 01 of the simplest state machine and the PSM has loadedthe corresponding byte at index 01h of the

Scan IF Operation24-26 Scan IF24.2.4 Scan IF Debug RegisterThe Scan IF peripheral has a SIFDEBUG register for debugging anddevelopment. Only the lowe

Scan IF Operation24-27Scan IF24.2.5 Scan IF InterruptsThe Scan IF has one interrupt vector for seven interrupt flags listed inTable 24−7. Each interr

Scan IF Operation24-28 Scan IF24.2.6 Using the Scan IF with LC SensorsSystems with LC sensors use a disk that is partially covered with a dampingmate

Scan IF Operation24-29Scan IF24.2.6.1 LC-Sensor Oscillation TestThe oscillation test tests if the amplitude of the oscillation after sensorexcitation

Addressing Modes3-15RISC 16-Bit CPU3.3.6 Indirect Autoincrement ModeThe indirect autoincrement mode is described in Table 3−9.Table 3−9.Indirect Autoi

Scan IF Operation24-30 Scan IF24.2.6.2 LC-Sensor Envelope TestThe envelop test measures the decay time of the oscillations after sensorexcitation. Th

Scan IF Operation24-31Scan IFFigure 24−17. LC Sensor Connections For The Envelope TestPowerSupplyTerminalsSIFCI0SIFCISIFCI1SIFCI2SIFCI3470 nFAVCCDVCC

Scan IF Operation24-32 Scan IF24.2.7 Using the Scan IF With Resistive SensorsSystems with GMRs use magnets on an impeller to measure rotation. Thedam

Scan IF Operation24-33Scan IF24.2.8 Quadrature DecodingThe Scan IF can be used to decode quadrature-encoded signals. Signals thatare 90° out of phase

Scan IF Operation24-34 Scan IFFigure 24−20. Quadrature Decoding State Diagram0010110100101101Correct State Transitions Erroneous State Transitions+1−

Scan IF Registers24-35Scan IF24.3 Scan IF RegistersThe Scan IF registers are listed in Table 24−9.Table 24−9.Scan IF RegistersRegister Short Form Re

Scan IF Registers24-36 Scan IFSIFDEBUG, Scan IF Debug Register, Write Mode15 14 13 12 11 10 9 8Reservedw w w w w w w w76543210Reserved SIFDEBUGxw w w

Scan IF Registers24-37Scan IFSIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written15 14 13 12 11 10 9 800 0 Index Of TSM Registerr r r r r

Scan IF Registers24-38 Scan IFSIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written15 14 13 12 11 10 9 80Active DAC Register 0 0 DAC Datar

Scan IF Registers24-39Scan IFSIFCNT, Scan IF Counter Register15 14 13 12 11 10 9 8SIFCNT2xr−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0)76543210SIFC

Register Bit Conventionsv Register Bit ConventionsEach register is shown with a key indicating the accessibility of the eachindividual bit, and the

Addressing Modes3-16 RISC 16-Bit CPU3.3.7 Immediate ModeThe immediate mode is described in Table 3−10.Table 3−10.Immediate Mode DescriptionAssembler C

Scan IF Registers24-40 Scan IFSIFCTL1, Scan IF Control Register 115 14 13 12 11 10 9 8SIFIE6 SIFIE5 SIFIE4 SIFIE3 SIFIE2 SIFIE1 SIFIE0 SIFIFG6rw−(0)

Scan IF Registers24-41Scan IFSIFIFG0Bit 2 SIF interrupt flag 0. This bit is set by the SIFxOUT conditions selected by theSIFIFGSETx bits. SIFIFG0 mus

Scan IF Registers24-42 Scan IFSIFCTL2, Scan IF Control Register 215 14 13 12 11 10 9 8SIFDACON SIFCAON SIFCAINV SIFCAX SIFCISEL SIFCACI3 SIFVSS SIFVC

Scan IF Registers24-43Scan IFSIFVCC2Bit 8 Mid-voltage generator0AVCC/2 generator is off1AVCC/2 generator is on if SIFSH = 0SIFSHBit 7 Sample-and-hold

Scan IF Registers24-44 Scan IFSIFCTL3, Scan IF Control Register 315 14 13 12 11 10 9 8SIFS2x SIFS1x SIFIS2x SIFIS1xrw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

Scan IF Registers24-45Scan IFSIFIFGSETxBits6-4SIFIFG0 interrupt flag source. These bits select when the SIFIFG0 flag is set.000 SIFIFG0 is set when S

Scan IF Registers24-46 Scan IFSIFCTL4, Scan IF Control Register 415 14 13 12 11 10 9 8SIFCNTRST SIFCNT2ENSIFCNT1ENMSIFCNT1ENPSIFQ7EN SIFQ6EN SIFDIV3B

Scan IF Registers24-47Scan IFSIFDIV3BxBits9-7TSM start trigger ACLK divider. These bits together with the SIFDIV3Ax bitsselect the division rate for

Scan IF Registers24-48 Scan IFSIFCTL5, Scan IF Control Register 515 14 13 12 11 10 9 8SIFCNT3xrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

Scan IF Registers24-49Scan IFSIFDACRx, Digital-To-Analog Converter Registers15 14 13 12 11 10 9 80 0 0 0 0 0 DAC Datar0 r0 r0 r0 r0 r0 rw rw76543210D

Instruction Set3-17RISC 16-Bit CPU3.4 Instruction SetThe complete MSP430 instruction set consists of 27 core instructions and 24emulated instructions.

Scan IF Registers24-50 Scan IFSIFTSMx, Scan IF Timing State Machine Registers15 14 13 12 11 10 9 8SIFREPEATx SIFACLK SIFSTOP SIFDACrw−(0) rw−(0) rw−(

Scan IF Registers24-51Scan IFSIFCLKONBit 5 High-frequency clock on. Setting this bit turns the high-frequency clock sourceon for this state when SIFA

Scan IF Registers24-52 Scan IFProcessing State Machine Table Entry (MSP430 Memory Location)76543210Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0Q7Bit 7 When Q7 = 1, SIFIFG

Instruction Set3-18 RISC 16-Bit CPU3.4.1 Double-Operand (Format I) InstructionsFigure 3−9 illustrates the double-operand instruction format.Figure 3−9

Instruction Set3-19RISC 16-Bit CPU3.4.2 Single-Operand (Format II) InstructionsFigure 3−10 illustrates the single-operand instruction format.Figure 3−

Instruction Set3-20 RISC 16-Bit CPU3.4.3 JumpsFigure 3−11 shows the conditional-jump instruction format.Figure 3−11. Jump Instruction FormatC 10-Bit P

Instruction Set3-21 RISC 16−Bit CPUADC[.W] Add carry to destinationADC.B Add carry to destinationSyntax ADC dst or ADC.W dstADC.B dstOper

Instruction Set3-22 RISC 16−Bit CPUADD[.W] Add source to destinationADD.B Add source to destinationSyntax ADD src,dst or ADD.W src,dstADD.B src,dstOp

Instruction Set3-23 RISC 16−Bit CPUADDC[.W] Add source and carry to destinationADDC.B Add source and carry to destinationSyntax ADDC src,dst or ADDC.

Instruction Set3-24 RISC 16−Bit CPUAND[.W] Source AND destinationAND.B Source AND destinationSyntax AND src,dst or AND.W src,dstAND.B src,dstOperation

Instruction Set3-25 RISC 16−Bit CPUBIC[.W] Clear bits in destinationBIC.B Clear bits in destinationSyntax BIC src,dst or BIC.W src,dstBIC.B src,dstOp

vi

Instruction Set3-26 RISC 16−Bit CPUBIS[.W] Set bits in destinationBIS.B Set bits in destinationSyntax BIS src,dst or BIS.W src,dstBIS.B src,dstOperati

Instruction Set3-27 RISC 16−Bit CPUBIT[.W] Test bits in destinationBIT.B Test bits in destinationSyntax BIT src,dst or BIT.W src,dstOperation src .AN

Instruction Set3-28 RISC 16−Bit CPU* BR, BRANCH Branch to ... destinationSyntax BR dstOperation dst −> PCEmulation MOV dst,PCDescription An

Instruction Set3-29 RISC 16−Bit CPUCALL SubroutineSyntax CALL dstOperation dst −> tmp dst is evaluated and storedSP − 2 −> SPPC −> @S

Instruction Set3-30 RISC 16−Bit CPU* CLR[.W] Clear destination* CLR.B Clear destinationSyntax CLR dst or CLR.W dstCLR.B dstOperation 0 −> dstEmulat

Instruction Set3-31 RISC 16−Bit CPU* CLRC Clear carry bitSyntax CLRCOperation 0 −> CEmulation BIC #1,SRDescription The carry bit (C) is cleared.

Instruction Set3-32 RISC 16−Bit CPU* CLRN Clear negative bitSyntax CLRNOperation 0 → Nor(.NOT.src .AND. dst −> dst)Emulation BIC #4,SRDescription

Instruction Set3-33 RISC 16−Bit CPU* CLRZ Clear zero bitSyntax CLRZOperation 0 → Zor(.NOT.src .AND. dst −> dst)Emulation BIC #2,SRDescription The

Instruction Set3-34 RISC 16−Bit CPUCMP[.W] Compare source and destinationCMP.B Compare source and destinationSyntax CMP src,dst or CMP.W src,dstCMP.

Instruction Set3-35 RISC 16−Bit CPU* DADC[.W] Add carry decimally to destination* DADC.B Add carry decimally to destinationSyntax DADC dst or D

Contentsvii Contents1 Introduction 1-11.1 Architecture 1-21.2 Flexible Clock System 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Set3-36 RISC 16−Bit CPUDADD[.W] Source and carry added decimally to destinationDADD.B Source and carry added decimally to destinationSynt

Instruction Set3-37 RISC 16−Bit CPU* DEC[.W] Decrement destination* DEC.B Decrement destinationSyntax DEC dst or DEC.W dstDEC.B dstOperation dst −

Instruction Set3-38 RISC 16−Bit CPU* DECD[.W] Double-decrement destination* DECD.B Double-decrement destinationSyntax DECD dst or DECD.W ds

Instruction Set3-39 RISC 16−Bit CPU* DINT Disable (general) interruptsSyntax DINTOperation 0 → GIEor(0FFF7h .AND. SR → SR / .NOT.src .AND. dst −>

Instruction Set3-40 RISC 16−Bit CPU* EINT Enable (general) interruptsSyntax EINTOperation 1 → GIEor(0008h .OR. SR −> SR / .src .OR. dst −> dst

Instruction Set3-41 RISC 16−Bit CPU* INC[.W] Increment destination* INC.B Increment destinationSyntax INC dst or INC.W dstINC.B dstOperation dst + 1

Instruction Set3-42 RISC 16−Bit CPU* INCD[.W] Double-increment destination* INCD.B Double-increment destinationSyntax INCD dst or INCD.W dstINCD.B dst

Instruction Set3-43 RISC 16−Bit CPU* INV[.W] Invert destination* INV.B Invert destinationSyntax INV dstINV.B dstOperation .NOT.dst −> dstEmulation

Instruction Set3-44 RISC 16−Bit CPUJC Jump if carry setJHS Jump if higher or sameSyntax JC labelJHS labelOperation If C = 1: PC + 2 × offset −> PCI

Instruction Set3-45 RISC 16−Bit CPUJEQ, JZ Jump if equal, jump if zeroSyntax JEQ label, JZ labelOperation If Z = 1: PC + 2 × offset −> PCIf Z = 0

Contentsviii3.3.5 Indirect Register Mode 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.6 Indirect

Instruction Set3-46 RISC 16−Bit CPUJGE Jump if greater or equalSyntax JGE labelOperation If (N .XOR. V) = 0 then jump to label: PC + 2 × offset −>

Instruction Set3-47 RISC 16−Bit CPUJL Jump if lessSyntax JL labelOperation If (N .XOR. V) = 1 then jump to label: PC + 2 × offset −> PCIf (N .XOR

Instruction Set3-48 RISC 16−Bit CPUJMP Jump unconditionallySyntax JMP labelOperation PC + 2 × offset −> PCDescription The 10-bit signed offset con

Instruction Set3-49 RISC 16−Bit CPUJN Jump if negativeSyntax JN labelOperation if N = 1: PC + 2 × offset −> PCif N = 0: execute following instruc

Instruction Set3-50 RISC 16−Bit CPUJNC Jump if carry not setJLO Jump if lowerSyntax JNC labelJLO labelOperation if C = 0: PC + 2 × offset −> PCif C

Instruction Set3-51 RISC 16−Bit CPUJNE Jump if not equalJNZ Jump if not zeroSyntax JNE labelJNZ labelOperation If Z = 0: PC + 2 × offset −> PCIf Z

Instruction Set3-52 RISC 16−Bit CPUMOV[.W] Move source to destinationMOV.B Move source to destinationSyntax MOV src,dst or MOV.W src,d

Instruction Set3-53 RISC 16−Bit CPU* NOP No operationSyntax NOPOperation NoneEmulation MOV #0, R3Description No operation is performed. The instruct

Instruction Set3-54 RISC 16−Bit CPU* POP[.W] Pop word from stack to destination* POP.B Pop byte from stack to destinationSyntax POP dstPOP.B dstOper

Instruction Set3-55 RISC 16−Bit CPUPUSH[.W] Push word onto stackPUSH.B Push byte onto stackSyntax PUSH src or PUSH.W srcPUSH.B srcOper

Contentsix 7 Hardware Multiplier 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Set3-56 RISC 16−Bit CPU* RET Return from subroutineSyntax RETOperation @SP→ PCSP + 2 → SPEmulation MOV @SP+,PCDescription The return addre

Instruction Set3-57 RISC 16−Bit CPURETI Return from interruptSyntax RETIOperation TOS → SRSP + 2 → SPTOS → PCSP + 2 → SPDescription The status regis

Instruction Set3-58 RISC 16−Bit CPU* RLA[.W] Rotate left arithmetically* RLA.B Rotate left arithmeticallySyntax RLA dst or RLA.W dstRLA.B dstOperatio

Instruction Set3-59 RISC 16−Bit CPU* RLC[.W] Rotate left through carry* RLC.B Rotate left through carrySyntax RLC dst or RLC.W dstRLC.B dstOperation

Instruction Set3-60 RISC 16−Bit CPURRA[.W] Rotate right arithmeticallyRRA.B Rotate right arithmeticallySyntax RRA dst or RRA.W dstRRA.B dstOperation M

Instruction Set3-61 RISC 16−Bit CPURRC[.W] Rotate right through carryRRC.B Rotate right through carrySyntax RRC dst or RRC.W dstRRC dstOperation C −&

Instruction Set3-62 RISC 16−Bit CPU* SBC[.W] Subtract source and borrow/.NOT. carry from destination* SBC.B Subtract source and borrow/.NOT. carry fro

Instruction Set3-63 RISC 16−Bit CPU* SETC Set carry bitSyntax SETCOperation 1 −> CEmulation BIS #1,SRDescription The carry bit (C) is set.Status

Instruction Set3-64 RISC 16−Bit CPU* SETN Set negative bitSyntax SETNOperation 1 −> NEmulation BIS #4,SRDescription The negative bit (N) is set.St

Instruction Set3-65 RISC 16−Bit CPU* SETZ Set zero bitSyntax SETZOperation 1 −> ZEmulation BIS #2,SRDescription The zero bit (Z) is set.Status Bit