Texas-instruments TSB12LV26 User Manual

2000 Bus SolutionsData Manual

viii4–10 Host Controller Control Register Description 4–13. . . . . . . . . . . . . . . . . . . . . . . . 4–11 Self-ID Count Register Description 4–14

1–11 Introduction1.1 DescriptionThe Texas Instruments TSB12LV26 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCIBus Powe

1–21.3 Related Documents•1394 Open Host Controller Interface Specification 1.0•P1394 Standard for a High Performance Serial Bus (IEEE 1394-1995)•P1394

2–12 Terminal DescriptionsThis section provides the terminal descriptions for the TSB12LV26. Figure 2–1 shows the signal assigned to eachterminal in t

2–2Table 2–1. Signals Sorted by Terminal NumberNO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME1 GND 26 PCI_AD25 51 PCI_SERR 76

2–3Table 2–2. Signal Names Sorted Alphanumerically to Terminal NumberTERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.CYCLEIN 78

2–4Table 2–4. PCI System TerminalsTERMINALI/ODESCRIPTIONNAME NO.I/ODESCRIPTIONG_RST 10 IGlobal power reset. This reset brings all of the TSB12LV26 int

2–5Table 2–5. PCI Address and Data TerminalsTERMINALI/ODESCRIPTIONNAME NO.I/ODESCRIPTIONPCI_AD31PCI_AD30PCI_AD29PCI_AD28PCI_AD27PCI_AD26PCI_AD25PCI_AD

2–6Table 2–6. PCI Interface Control TerminalsTERMINALI/ODESCRIPTIONNAME NO.I/ODESCRIPTIONPCI_C/BE0PCI_C/BE1PCI_C/BE2PCI_C/BE365534128I/OPCI bus comman

2–7Table 2–7. IEEE 1394 PHY/Link TerminalsTERMINALI/ODESCRIPTIONNAME NO.I/ODESCRIPTIONPHY_CTL1PHY_CTL09293I/OPHY-link interface control. These bidirec

Printed in U.S.A., 03/00 SLLS366A

2–8

3–13 TSB12LV26 Controller Programming ModelThis section describes the internal registers used to program the TSB12LV26. All registers are detailed in

3–2InternalRegistersISO TransmitContextsAsync TransmitContextsPhysical DMA& ResponsePCITargetSMPHYRegisterAccess& StatusMonitorCentralArbiter&

3–33.1 PCI Configuration RegistersThe TSB12LV26 is a single-function PCI device. The configuration header is compliant with the PCI Local BusSpecifica

3–43.3 Device ID RegisterThe device ID register contains a value assigned to the TSB12LV26 by Texas Instruments. The device identificationfor the TSB1

3–53.5 Status RegisterThe status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to thedefinitions in t

3–63.6 Class Code and Revision ID RegisterThe class code and revision ID register categorizes the TSB12LV26 as a serial bus controller (0Ch), controll

3–73.8 Header Type and BIST RegisterThe header type and BIST register indicates the TSB12LV26 PCI header type, and indicates no built-in self test. Se

3–83.10 TI Extension Base Address RegisterThe TI extension base address register is programmed with a base address referencing the memory-mapped TIext

3–93.12 Power Management Capabilities Pointer RegisterThe power management capabilities pointer register provides a pointer into the PCI configuration

TSB12LV26OHCI-Lynx PCI-Based IEEE 1394Host ControllerData ManualLiterature Number: SLLS366AMarch 2000Printed on Recycled Paper

3–103.14 MIN_GNT and MAX_LAT RegisterThe MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of bits 15–8 of thelate

3–113.16 Capability ID and Next Item Pointer RegisterThe capability ID and next item pointer register identifies the linked list capability item and p

3–123.17 Power Management Capabilities RegisterThe power management capabilities register indicates the capabilities of the TSB12LV26 related to PCI p

3–133.18 Power Management Control and Status RegisterThe power management control and status register implements the control and status of the PCI pow

3–143.20 Miscellaneous Configuration RegisterThe miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3–17

3–153.21 Link Enhancement Control RegisterThe link enhancement control register implements TI proprietary bits that are initialized by software or by

3–16Table 3–18. Link Enhancement Control Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION1 enab_accel R/WEnable acceleration enhanceme

3–173.23 GPIO Control RegisterThe GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3–20 for acomplete de

3–18

4–14 OHCI RegistersThe OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a2-Kbyte region of memor

IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or servic

4–2Table 4–1. OHCI Register Map (Continued)DMA CONTEXT REGISTER NAME ABBREVIATION OFFSETSelf ID Reserved — 60hSelf ID buffer SelfIDBuffer 64hSelf ID

4–3Table 4–1. OHCI Register Map (Continued)DMA CONTEXT REGISTER NAME ABBREVIATION OFFSETAsynchronous context controlContextControlSet 180hAsychronous

4–44.1 OHCI Version RegisterThis register indicates the OHCI version support, and whether or not the serial ROM is present. See Table 4–2 fora complet

4–54.2 GUID ROM RegisterThe GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCIversion registe

4–64.3 Asynchronous Transmit Retries RegisterThe asynchronous transmit retries register indicates the number of times the TSB12LV26 attempts a retry f

4–74.5 CSR Compare RegisterThe CSR compare register is used to access the bus management CSR registers from the host throughcompare-swap operations. T

4–84.7 Configuration ROM Header RegisterThe configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offs

4–94.9 Bus Options RegisterThe bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4–7 for a completedescripti

4–104.10 GUID High RegisterThe GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the thirdquadlet in t

4–114.12 Configuration ROM Mapping RegisterThe configuration ROM mapping register contains the start address within system memory that maps to the sta

iiiContentsSection Title Page1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–124.14 Posted Write Address High RegisterThe posted write address high register is used to communicate error information if a write request is poste

4–134.16 Host Controller Control RegisterThe host controller control set/clear register pair provides flags for controlling the TSB12LV26. See Table 4

4–144.17 Self-ID Buffer Pointer RegisterThe self-ID buffer pointer register points to the 2-Kbyte aligned base address of the buffer in host memory wh

4–154.19 Isochronous Receive Channel Mask High RegisterThe isochronous receive channel mask high set/clear register is used to enable packet receives

4–16Table 4–12. Isochronous Receive Channel Mask High Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION6 isoChannel38 RSC When this bit

4–174.21 Interrupt Event RegisterThe interrupt event set/clear register reflects the state of the various TSB12LV26 interrupt sources. The interrupt b

4–18Table 4–14. Interrupt Event Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION17 busReset RSCU Indicates that the PHY chip has enter

4–194.22 Interrupt Mask RegisterThe interrupt mask set/clear register is used to enable the various TSB12LV26 interrupt sources. Reads from eitherthe

4–204.23 Isochronous Transmit Interrupt Event RegisterThe isochronous transmit interrupt event set/clear register reflects the interrupt state of the

4–214.24 Isochronous Transmit Interrupt Mask RegisterThe isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrup

iv4.7 Configuration ROM Header Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Bus Identification Register 4–8. . . . . . . . .

4–224.25 Isochronous Receive Interrupt Event RegisterThe isochronous receive interrupt event set/clear register reflects the interrupt state of the is

4–234.27 Fairness Control RegisterThe fairness control register provides a mechanism by which software can direct the host controller to transmitmulti

4–244.28 Link Control RegisterThe link control set/clear register provides the control flags that enable and configure the link core protocol portions

4–254.29 Node Identification RegisterThe node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indica

4–264.30 PHY Layer Control RegisterThe PHY layer control register is used to read or write a PHY register. See Table 4–21 for a complete description o

4–274.31 Isochronous Cycle Timer RegisterThe isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV26 is cyc

4–284.32 Asynchronous Request Filter High RegisterThe asynchronous request filter high set/clear register is used to enable asynchronous receive reque

4–29Table 4–23. Asynchronous Request Filter High Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION18 asynReqResource50 RSCIf this bit i

4–304.33 Asynchronous Request Filter Low RegisterThe asynchronous request filter low set/clear register is used to enable asynchronous receive request

4–314.34 Physical Request Filter High RegisterThe physical request filter high set/clear register is used to enable physical receive requests on a per

v7.5 Switching Characteristics for PHY-Link Interface 7–3. . . . . . . . . . . . . . . . . 8 Mechanical Information 8–1. . . . . . . . . . . . . . . .

4–32Table 4–25. Physical Request Filter High Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION19 physReqResource51 RSCIf this bit is se

4–334.35 Physical Request Filter Low RegisterThe physical request filter low set/clear register is used to enable physical receive requests on a per-n

4–344.36 Physical Upper Bound Register (Optional Register)The physical upper bound register is an optional register and is not implemented. It returns

4–354.37 Asynchronous Context Control RegisterThe asynchronous context control set/clear register controls the state and indicates status of the DMA c

4–364.38 Asynchronous Context Command Pointer RegisterThe asynchronous context command pointer register contains a pointer to the address of the first

4–374.39 Isochronous Transmit Context Control RegisterThe isochronous transmit context control set/clear register controls options, state, and status

4–384.40 Isochronous Transmit Context Command Pointer RegisterThe isochronous transmit context command pointer register contains a pointer to the addr

4–39Table 4–30. Isochronous Receive Context Control Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION29 cycleMatchEnable RSCUWhen this

4–404.42 Isochronous Receive Context Command Pointer RegisterThe isochronous receive context command pointer register contains a pointer to the addres

4–414.43 Isochronous Receive Context Match RegisterThe isochronous receive context match register is used to start an isochronous receive context runn

viList of IllustrationsFigure Title Page2–1 Terminal Assignments 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–42

5–15 GPIO InterfaceThe general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up asgeneral-purpose inputs and

5–2

6–16 Serial ROM InterfaceThe TSB12LV26 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCIconfiguration reg

6–2Table 6–2. Serial ROM MapBYTEADDRESSBYTE DESCRIPTION00 PCI maximum latency (0h) PCI_minimum grant (0h)01 PCI vendor ID02 PCI vendor ID (msbyte)03 P

7–17 Electrical Characteristics7.1 Absolute Maximum Ratings Over Operating Temperature Ranges†Supply voltage range, VCC –0.5 V to 3.6 V. . . . . . .

7–27.2 Recommended Operating ConditionsOPERATION MIN NOM MAX UNITVCCCore voltage Commercial 3.3 V 3 3.3 3.6 VVCCPPCI I/O clamping voltageCommercial3.3

7–37.3 Electrical Characteristics Over Recommended Operating Conditions (unlessotherwise noted)OPERATIONTESTCONDITIONSMIN MAX UNITPCIIOH = – 0.5 mA 0.

7–4

8–18 Mechanical InformationThe TSB12LV26 is packaged in a 100-terminal PZ package. The following shows the mechanical dimensions for thePZ package.PZ

viiList of TablesTable Title Page2–1 Signals Sorted by Terminal Number 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Signal Nam

8–2

IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or servic