Texas-instruments MSP430x1xx User Manual

2000 Mixed Signal ProductsUser’s GuideSLAU049

Contentsx15.2.1 ADC Core 15-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2

Hardware Multiplier Software Restrictions6-126.5.3 Hardware Multiplier Software Restrictions—MACSThe multiplier does not automatically detect underflo

7-1Basic Clock Module Basic Clock ModuleThis chapter discusses the Basic Clock Module used in the MSP430x1xxfamilies.Topic Page7.1 Basic Clock Module

7-27.1 Basic Clock ModuleThe Basic Clock Module (shown in Figure 7–1) follows the major targets of lowsystem cost and low power consumption. Using th

7-3Basic Clock ModuleThe Basic Clock Module includes two or three clock sources:LFXT1CLK low-frequency/high-frequency clock source. One oscillatortha

LFXT1 and XT2 Oscillators7-47.2 LFXT1 and XT2 OscillatorsThe Basic Clock Module includes the LFXT1 oscillator and, in some configura-tions, a second X

LFXT1 and XT2 Oscillators7-5Basic Clock ModuleFigure 7–3. Off Signals for the LFXT1 OscillatorXT2XTSOscOffCPUOffSELM.1SELM.0SCG1SELSXT2 Is an Internal

LFXT1 and XT2 Oscillators7-67.2.3 Oscillator Fault DetectionAn analog circuit controls the operation of oscillators LFXT1 and XT2 and flagsan oscillat

LFXT1 and XT2 Oscillators7-7Basic Clock ModuleAfter applying VCC the oscillator fault signal (XT_OscFault) becomes active.The XT_OscFault signal becom

LFXT1 and XT2 Oscillators7-8Figure 7–8. Oscillator Fault in Oscillator Error Condition at Start-UpVCCXT2CLKLFXT1CLKXT_OscFaultXT1Off/XT2Off7.2.4 Selec

LFXT1 and XT2 Oscillators7-9Basic Clock ModuleFigure 7–9. NMI/OSCFault Interrupt HandlerStart of NMI Interrupt HandlerReset by HW:OFIE, NMIE, ACCIEOFI

Contentsxi ContentsB.2 Instruction Set Description B-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digitally-Controlled Oscillator (DCO)7-107.3 Digitally-Controlled Oscillator (DCO)The DCO is an integrated RC-type oscillator in the Basic Clock Modul

Digitally-Controlled Oscillator (DCO)7-11Basic Clock ModuleFigure 7–11. Principle Period Steps of the DCOfDCOCLKNominal0 1 2 3 4 5 6 7 DCOFive bits (S

Digitally-Controlled Oscillator (DCO)7-127.3.1 Operation of the DCO ModulatorThe modulator is intended to reduce a long accumulating period variation

Digitally-Controlled Oscillator (DCO)7-13Basic Clock ModuleThe user should consider two factors when reviewing the timing accuracy gen-erated from the

Basic Clock Module Operating Modes7-147.4 Basic Clock Module Operating Modes Control bits SCG0, SCG1, OscOff, and CPUOff in the status register config

Features for Low-Power Applications7-15Basic Clock Module7.4.3 Basic Clock Features for Low-Power ApplicationsConflicting requirements typically exist

Features for Low-Power Applications7-16b) In x13x and x14x devices, the XT2 oscillator can also be used: XT2Offis resetBIC.B #XT2Off,&BCSCTL1 ; Re

Features for Low-Power Applications7-17Basic Clock ModuleJNC RetestBIC.B #OFIFG,&IFG1 ; Clear osc. fault int. flagBIS.B #(SELM1+SELM0),&

Basic Clock Module Control Registers 7-187.5 Basic Clock Module Control Registers The Basic Clock Module is configured using control registers DCOCTL,

Basic Clock Module Control Registers7-19Basic Clock ModuleBit6, XTS: The LFXT1 oscillator operates with a low-frequency clockcrystal or with a high-fr

Running Title—Attribute ReferencexiiFigures2–1 MSP430 System Configuration 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Clock Module Control Registers7-207.5.3 Special-Function Register BitsThe Basic Clock Module affects two bits in the special-function registersO

8-1Digital I/O Configuration Digital I/O ConfigurationThis chapter describes the digital I/O configuration.Topic Page8.1 Introduction 8-2. . . . . . .

Introduction8-28.1 IntroductionThe general-purpose I/O ports of the MSP430 are designed to give maximumflexibility. Each I/O line is individually conf

Ports P1, P28-3Digital I/O Configuration8.2 Ports P1, P2Each of the general-purpose ports P1 and P2 contain 8 general-purpose I/Olines and all of the

Ports P1, P28-48.2.1 Port P1, Port P2 Control RegistersThe seven control registers give maximum digital input/output configurationflexibility:All indi

Ports P1, P28-5Digital I/O Configuration8.2.1.2 Output Registers P1OUT, P2OUTEach output register shows the information of the output buffer. The outp

Ports P1, P28-68.2.1.5 Interrupt Edge Select P1IES, P2IESEach interrupt edge select register contains a bit for each corresponding I/Opin to select wh

Ports P1, P28-7Digital I/O ConfigurationNote: Function Select With P1SEL, P2SELThe interrupt-edge-select circuitry is disabled if control bit PnSEL.x

Ports P1, P28-88.2.3 Port P1, P2 Interrupt Control FunctionsPorts P1 and P2 use eight bits for interrupt flags, eight bits to enable interrupts,eight

Ports P3, P4, P5, P68-9Digital I/O Configuration8.3 Ports P3, P4, P5, P6General-purpose ports P3–P6 function as shown in Figure 8–3. Each pin canbe se

Figuresxiii Figures7–7 Oscillator Fault in Oscillator Error Condition 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ports P3, P4, P5, P68-10Table 8–3.Port P3–P6 RegistersRegister Short Form Address Register Type Initial StateInputP3IN 018h Read only – – – – –P4IN 01

Ports P3, P4, P5, P68-11Digital I/O Configuration8.3.1.4 Function Select Registers PnSELPorts P3–P6 pins are often multiplexed with other peripheral m

8-12

9-1Watchdog Timer Watchdog TimerThis chapter discusses the Watchdog Timer.Topic Page9.1 The Watchdog Timer 9-2. . . . . . . . . . . . . . . . . . . .

The Watchdog Timer9-29.1 The Watchdog TimerThe primary function of the watchdog-timer module (WDT) is to perform acontrolled-system restart after a so

The Watchdog Timer9-3Watchdog Timer9.1.1 Watchdog Timer RegisterThe watchdog-timer counter (WDTCNT) is a 16-bit up-counter that is notdirectly accessi

The Watchdog Timer9-4Bit 5: The NMI bit selects the function of the RST/NMI input pin. It iscleared by the PUC signal.NMI = 0: The RST/NMI input works

The Watchdog Timer9-5Watchdog Timer9.1.2 Watchdog Timer Interrupt Control FunctionsThe Watchdog Timer (WDT) uses two bits in the SFRs for interrupt co

The Watchdog Timer9-6When the module is used in watchdog mode, the software should periodicallyreset the WDTCNT by writing a 1 to bit CNTCL of WDTCTL

The Watchdog Timer9-7Watchdog Timer9.1.3.4 Software ExampleThe following example illustrates the watchdog-reset operation.; After RESET or power–up, t

Figuresxiv10–32 Vector Word Register 10-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-8

10-1Timer_A Timer_AThis section describes the basic functions of the MSP430 general-purpose16-bit Timer_A. All capture/compare blocks (CCR) are identi

Introduction10-210.1 IntroductionTimer_A is an extremely versatile timer made up of :16-bit counter with 4 operating modesSelectable and configurable

Introduction10-3Timer_AFigure 10–1. Timer_A Block DiagramInputDividerCLK116-Bit TimerTPSSEL0TPSSEL1TACLKACLKSMCLK0123RCINCLKID1ID0150DataTimer ClockPO

Timer_A Operation10-410.2 Timer_A OperationThe 16-bit timer has 4 modes of operation selectable with the MC0 and MC1bits in the TACTL register. The ti

Timer_A Operation10-5Timer_A10.2.2 Clock Source Select and DividerThe timer clock can be sourced from internal clocks (i.e. ACLK or SMCLK) orfrom an e

Timer_A Operation10-610.2.3 Starting the TimerThe timer may be started or restarted in a variety of ways:Release Halt Mode: The timer counts in the se

Timer Modes10-7Timer_A10.3 Timer Modes10.3.1 Timer—Stop ModeStopping and starting the timer is done simply by changing the mode controlbits (MCx). The

Timer Modes10-810.3.2.1 Timer in Up Mode—Changing the Period Register CCR0 ValueChanging the timer period register CCR0 while the timer is running can

Timer Modes10-9Timer_A10.3.3 Timer—Continuous ModeThe continuous mode is used if the timer period of 65,536 clock cycles is usedfor the application. A

Figuresxv Figures12–16 USART Control Register UCTL 12-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Modes10-1010.3.3.1 Timer—Use of the Continuous ModeThe continuous mode can be used to generate time intervals for theapplication software. Each

Timer Modes10-11Timer_AThe up/down mode also supports applications that require dead timesbetween output signals. For example, to avoid overload condi

Timer Modes10-12In up/down mode, the interrupt flags (CCIFG0 and TAIFG) are set at equal timeintervals (Figure 10–15). Each flag is set only once duri

Timer Modes10-13Timer_A10.4 Capture/Compare BlocksThree or five (depending on device) identical capture/compare blocks (shownin Figure 10–17) provide

Timer Modes10-1410.4.1 Capture/Compare Block—Capture ModeThe capture mode is selected if the mode bit CAPx, located in control wordCCTLx, is set. The

Timer Modes10-15Timer_AFigure 10–19. Capture Signaln-2TimerClockTimerSetCCIFGxCapturen+1CCIxn-1n+2 n+3 n+4 n+5 n+6nApplications with slow timer clocks

Timer Modes10-16Figure 10–20. Capture CycleSecondCaptureTakenCOV = 1CaptureTakenNoCaptureTakenReadTakenCaptureClear Bit COVin Register CCTLIdleIdleCap

Timer Modes10-17Timer_A10.4.1.1 Capture/Compare Block, Capture Mode—Capture Initiated by SoftwareIn addition to internal and external signals, capture

Timer Modes10-1810.4.2 Capture/Compare Block—Compare ModeThe compare mode is selected if the CAPx bit, located in control word CCTLx,is reset. In comp

Timer Modes10-19Timer_A10.5 The Output UnitEach capture/compare block contains an output unit shown in Figure 10–22.The output unit is used to generat

Figuresxvi14–15 Timing for Measuring a Current Source 14-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–16 A/D C

Timer Modes10-2010.5.1 Output Unit—Output ModesThe output modes are defined by the OMx bits and are discussed below. TheOUTx signal is changed with th

Timer Modes10-21Timer_A10.5.2 Output Control BlockThe output control block prepares the value of the OUTx signal, which islatched into the OUTx flip-f

Timer Modes10-22Table 10–2.State of OUTx at Next Rising Edge of Timer ClockMode EQU0 EQUx D0 x x x(OUTx bit)1 xx01OUTx (no change)1 (set)2 00110101OUT

Timer Modes10-23Timer_AFigure 10–24. Output Examples—Timer in Up ModeExample, EQU1 Used0FFFFhCCR0CCR10hEQU0 EQU1 EQU0 EQU1 EQU0Output Mode 1: SetOutpu

Timer_A Registers10-2410.5.3.3 Output Examples—Timer in Up/Down ModeThe OUTx signal changes when the timer equals CCRx in either countdirection and

Timer_A Registers10-25Timer_A10.6.1 Timer_A Control Register TACTLThe timer and timer operation control bits are located in the timer controlregister

Timer_A Registers10-26Table 10–5.Input Clock Divider Control BitsID1 ID0 Operation Description0 0 /1 Input clock source is passed to the timer.0 1 /2

Timer_A Registers10-27Timer_ANote: Modifying Timer A Register TARWhen ACLK, SMCLK, or the external clock TACLK or INCLK is selected forthe timer clock

Timer_A Registers10-28Bit 3: Capture/compare input signal CCIx:The selected input signal (CCIxA, CCIxB, VCC. or GND) can beread by this bit. See Figur

Timer_A Registers10-29Timer_ABits 14, 15: Capture mode bits:Table 10–8 describes the capture mode selections.Table 10–8.Capture/Compare Control Regist

Figuresxvii FiguresC–6 Block Diagram of the Timing Generator in the Flash Memory Module C-7. . . . . . . . . . . . . . . . C–7 Basic Flash EEPROM Mo

Timer_A Registers10-3010.6.4.2 Vector Word, TAIFG, CCIFG1 to CCIFG4 FlagsThe CCIFGx (other than CCIFG0) and TAIFG interrupt flags are prioritized andc

Timer_A Registers10-31Timer_ATable 10–9.Vector Register TAIV DescriptionInterruptPriorityInterrupt Source Short FormVector RegisterTAIV ContentsHighes

Timer_A Registers10-32JMP TIMMOD1 ; Vector 2: Module 1 2JMP TIMMOD2 ; Vector 4: Module 2 2JMP TIMMOD3 ; Vector 6: Module 3 2JMP TIMMOD4 ; Vector 8: Mo

Timer_A UART10-33Timer_A10.6.4.4 Timing LimitsWith the TAIV register and the previous software, the shortest repetitive timedistance tCRmin between tw

Timer_A UART10-34The receive feature uses one capture/compare function to shift pin data intomemory through bit SCCIx. The receive start time is recog

Timer_A UART10-35Timer_AOne capture/compare block is used when half-duplex communication modeis desired. Two capture/compare blocks are used for full-

10-36

11-1Timer_B Timer_BThis section describes the basic functions of the MSP430 general-purpose16-bit Timer_B. Timer_B implementation differs among MSP430

Introduction11-211.1 IntroductionTimer_B is an extremely versatile timer made up of :16-bit counter with 4 operating modes and four selectable lengths

Introduction11-3Timer_Beach CCRx register to the corresponding compare latch (TBCLx) is user-selectable to be either immediate, or on a timer event. S

Running Title—Attribute ReferencexviiiTables3–1 Interrupt Control Bits in SFRs 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction11-4Figure 11–1. Timer_B Block DiagramInputDividerCLK116-Bit TimerTPSSEL0TPSSEL1TBCLKACLKSMCLK0123RCINCLKID1ID0150DataTimer ClockPOR/CLRMo

Timer_B Operation11-5Timer_B11.2 Timer_B OperationThe 16-bit timer has four modes of operation selectable with the MC0 and MC1bits in the TBCTL regist

Timer_B Operation11-6Table 11–1. Timer ModesMode ControlMC1 MC0Mode Description0 0 Stop The timer is halted.0 1 Up The timer counts upward until its v

Timer_B Operation11-7Timer_BFigure 11–4. Schematic of Clock Source Select and Input DividerTQ16-Bit Timer ClockID1CTQCTQCID0POR CLR00110101Pass1/21/41

Timer Modes11-811.3 Timer Modes11.3.1 Timer—Stop ModeStopping and starting the timer is done simply by changing the mode controlbits (MCx). The value

Timer Modes11-9Timer_B11.3.2.1 Timer in Up Mode—Changing the Period Register TBCL0 Value, Immediate Mode for TBCL0Changing the timer period register T

Timer Modes11-10Figure 11–8. New Period < Old PeriodTBCL0old = 5TBCL0new = 2TimerRegister54321001234501230120120152012 3 450123 401 201 20152TimerR

Timer Modes11-11Timer_BThe TBIFG flag is set when the timer counts from TBR(max) to zero. Theinterrupt flag is set independently of the corresponding

Timer Modes11-1211.3.4 Timer—Up/Down ModeThe up/down mode is used if the timer period must be different from theTBR(max) clock cycles, and if symmetri

Timer Modes11-13Timer_BThe count direction is always latched with a flip-flop (Figure 11–14). This isuseful because it allows the user to stop the tim

Tablesxix Tables10–7 Capture/Compare Control Register Output Mode 10-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–8 Capture/

Timer Modes11-14those in the up mode. See Section 11.3.2.1 for details. However, if the timeris counting in the down direction when TBCL0 is updated,

Timer Modes11-15Timer_B11.4 Capture/Compare BlocksSeven identical capture/compare blocks (shown in Figure 11–17) provideflexible control for real-time

Timer Modes11-1611.4.1 Capture/Compare Block—Capture ModeThe capture mode is selected if the mode bit CAPx, located in control wordCCTLx, is set. The

Timer Modes11-17Timer_BApplications with slow timer clocks can use the nonsynchronized capturesignal. In this scenario the software can validate the d

Timer Modes11-18Overflow bit COVx is reset by the software as described in the followingexample:; Software example for the handling of captured data;

Timer Modes11-19Timer_BFigure 11–21.Software Capture ExampleCaptureModeCCISx0CCISx1CCIxACCIxBGND0123VCCCCMx1 CCMx0CMPxCCIxCCISx1CCISx0CCIxCaptureCaptu

Timer Modes11-20Interrupt flag CCIFGx, located in control word CCTLx, is set.An interrupt is requested if interrupt enable bits CCIEx and GIE are set.

Timer Modes11-21Timer_BThe groupings and load conditions are summarized below in Table 11–2Table 11–2. Shadow Register Operating ModesTBCLGRPCLLDx Fro

Timer Modes11-22Timer_BTable 11–2. Shadow Register Operating Modes (Continued)TBCLGRPCLLDx FromLowestCCTLx inCounterModeLoad ConditionsTBCLGRPCCTLx i

The Output Unit11-23Timer_B11.5 The Output UnitEach capture/compare block contains an output unit shown in Figure 11–22.The output unit is used to gen

IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or servic

Running Title—Attribute ReferencexxExamples12–1 4800 Baud 12-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-2411.5.1 Output Unit – Output ModesThe output modes are defined by the OMx bits and are discussed below. TheOUTx signal is changed with the rising

11-25Timer_B11.5.2 Output Control BlockThe output control block prepares the value of the OUTx signal, which islatched into the OUTx flip-flop with t

11-26Table 11–3. State of OUTx at Next Rising Edge of Timer ClockMode EQU0 EQUx D0 x x x(OUTx bit)1 xx01OUTx (no change)1 (set)2 00110101OUTx (no cha

11-27Timer_BFigure 11–24.Output Examples—Timer in Up ModeExample, EQU1 UsedTBR(max)TBCL0TBCL10hEQU0 EQU1 EQU0 EQU1 EQU0Output Mode 1: SetOutput Mode

11-2811.5.3.3 Output Examples – Timer in Up/Down ModeThe OUTx signal changes when the timer equals TBCLx in either countdirection and when the time

Timer_B Registers11-29Timer_B11.6 Timer_B RegistersThe Timer_B registers, described in Table 11–4, are word structured and mustbe accessed using word

Timer_B Registers11-30Bit 2: Timer clear (CLR) bit. The timer and input divider are reset with thePOR signal, or if bit CLR is set. The CLR bit is aut

Timer_B Registers11-31Timer_BBit 10: UnusedBits 11, 12: Configure 16-bit timer (TBR) for 8-bit, 10-bit, 12-bit, or 16-bitoperationCNTL = 0: 16-bit len

Timer_B Registers11-32Note: Changing Timer_B Control BitsIf the timer operation is modified by the control bits in the TBCTL register, thetimer should

Timer_B Registers11-33Timer_BBit 0: Capture/compare interrupt flag CCIFGxCapture mode:If set, it indicates that a timer value was captured in theCCRx

Running Title—Attribute Referencexxi ContentsNotes, Cautions, and WarningsNote: If desired, software can cause a PUC by simply writing to the watchd

Timer_B Registers11-34Table 11–8. Capture/Compare Control Register Output ModeBit ValueOutput Mode Description0 Output only The OUTx signal reflects t

Timer_B Registers11-35Timer_BTable 11–9. Capture/Compare Control Register Capture ModeBitValueCapture Mode Description0 Disabled The capture mode is d

Timer_B Registers11-3611.6.4.2 Vector Word, TBIFG, CCIFG1 to CCIFGx FlagsThe CCIFGx (other than CCIFG0) and TBIFG interrupt flags are prioritized andc

Timer_B Registers11-37Timer_BTable 11–10. Vector Register TBIV DescriptionInterruptPriorityInterrupt Source Short FormVector RegisterTBIV ContentsHigh

Timer_B Registers11-3811.6.4.3 Timer Interrupt Vector Register, Software Example, Timer_B7The following software example describes the use of vector w

Timer_B Registers11-39Timer_B11.6.4.4 Timer Interrupt Vector Register, Software Example, Timer_B3The following software example describes the use of v

Timer_B Registers11-40The software overhead for different interrupt sources includes interruptlatency and return-from-interrupt cycles (but not the ta

12-1USART Peripheral Interface, UART Mode USART Peripheral Interface, UART ModeThe universal synchronous/asynchronous receive/transmit (USART) serial-

USART Peripheral Interface12-212.1 USART Peripheral InterfaceThe USART peripheral interface connects to the CPU as a byte peripheralmodule. It connect

USART Peripheral Interface, UART Mode12-3USART Peripheral Interface, UART Mode12.2 USART Peripheral Interface, UART ModeThe USART peripheral interface

ContentsxxiiCaution! The following must be considered when turning the ADC12 and voltage reference on or off. 15-21. . . . . . . . . . . . . . . . . .

Asynchronous Operation12-412.3 Asynchronous OperationIn the asynchronous mode, the receiver synchronizes itself to frames but theexternal transmitting

Asynchronous Operation12-5USART Peripheral Interface, UART Mode12.3.2 Baud Rate Generation in Asynchronous Communication FormatBaud rate generation in

Asynchronous Operation12-6Figure 12–6. MSP430 Baud Rate Generation. Example for n or n + 1 Clock Periods0SSEL0SSEL1UCLKIACLK12315-Bit Prescaler/Divide

Asynchronous Operation12-7USART Peripheral Interface, UART Mode12.3.3 Asynchronous Communication FormatsThe USART module supports two multiprocessor c

Asynchronous Operation12-8When two stop bits are used for the idle line, as shown in Figure 12–8, thesecond one is counted as the first mark bit of th

Asynchronous Operation12-9USART Peripheral Interface, UART ModeThe following procedure sends out an idle frame to identify an addresscharacter:1) Set

Asynchronous Operation12-10Figure 12–11.Address-Bit Multiprocessor FormatST Address SP ST Data SP ST Data SPBlock of FramesIdle Periods of No Signific

Interrupt and Enable Functions12-11USART Peripheral Interface, UART Mode12.4 Interrupt and Enable FunctionsThe USART peripheral interface serves two m

Interrupt and Enable Functions12-1212.4.2 USART Transmit Enable BitThe transmit enable bit UTXE, shown in Figure 12–13, enables or disables acharacter

Interrupt and Enable Functions12-13USART Peripheral Interface, UART Mode12.4.3 USART Receive Interrupt OperationIn the receive interrupt operation, sh

1-1Introduction IntroductionThis chapter outlines the features and capabilities of the Texas Instruments(TI) MSP430x1xx family of microcontrollers.Th

Interrupt and Enable Functions12-1412.4.4 USART Transmit Interrupt OperationIn the transmit interrupt operation, shown in Figure 12–15, the transmitin

Control and Status Registers12-15USART Peripheral Interface, UART Mode12.5 Control and Status RegistersThe USART control and status registers are byte

Control and Status Registers12-1612.5.1 USART Control Register UCTLThe information stored in the USART control register (UCTL), shown inFigure 12–16,

Control and Status Registers12-17USART Peripheral Interface, UART ModeCHAR = 0: 7-bit dataCHAR = 1: 8-bit dataBit 5: Number of stop bitsThis bit deter

Control and Status Registers12-18Bit 3: The receive-start edge-control bit, if set, requests a receiveinterrupt service. For a successful interrupt se

Control and Status Registers12-19USART Peripheral Interface, UART ModeRXWake is reset by accessing the receive buffer (URXBUF), bya USART software res

Control and Status Registers12-20calculation. The flag is disabled if parity generation anddetection are not enabled. In this case the flag is read as

Control and Status Registers12-21USART Peripheral Interface, UART ModeThe timing of the running bit is expanded by one clock cycle of the baud-rate-di

Utilizing Features of Low-Power Modes12-22Note: Writing to UTXBUFWriting data to the transmit-data buffer must only be done if buffer UTXBUFis empty;

Utilizing Features of Low-Power Modes12-23USART Peripheral Interface, UART Mode12.6.1.1 Start ConditionsThe URXD signal feeds into the USART module by

Features and Capabilities1-21.1 Features and CapabilitiesThe TI MSP430x1xx family of controllers has the following features andcapabilities:Ultralow-p

Utilizing Features of Low-Power Modes12-24*********************************************************** Interrupt handler for frame start condition a

Baud Rate Considerations12-25USART Peripheral Interface, UART Mode12.6.3 Support of Multiprocessor Modes for Reduced Use of MSP430 ResourcesCommunicat

Baud Rate Considerations12-26Figure 12–27. MSP430 Transmit Bit Timing0 12345 6789101112t0t1t2t3t4t5t6t7t8t9t10t11t12itiST D0 D6 D7MarkSpace[2nd Stop B

Baud Rate Considerations12-27USART Peripheral Interface, UART ModeExample 12–3. Error Example for 2400 BaudThe following data are assumed:Baud rate =

Baud Rate Considerations12-28Table 12–6.Commonly Used Baud Rates, Baud Rate Data, and ErrorsDivide by ACLK (32,768 Hz) MCLK (1,048,576 Hz)BaudRateACLK

Baud Rate Considerations12-29USART Peripheral Interface, UART ModeFigure 12–29. Synchronization Error1234560it0ttarget781t129 10 11 12 13 14 1 2 3 4 5

Baud Rate Considerations12-30Data bit D1 Error [%]baud rateBRCLK[2x(1 6)(2 UBR 1)]–1–2 100% 0.29%Data bit D2 Error [%]baud rateBRCLK[2x(1 6)(3 UBR 2)]

13-1USART Peripheral Interface, SPI Mode USART Peripheral Interface, SPI ModeThe universal synchronous/asynchronous receive/transmit (USART) serial-co

13-213.1 USART Peripheral InterfaceThe USART peripheral interface connects to the CPU as a byte-peripheralmodule. It connects the MSP430 to the exter

13-3USART Peripheral Interface, SPI Mode13.2 USART Peripheral Interface, SPI ModeThe USART peripheral interface is a serial channel that shifts a ser

11x Devices1-3IntroductionVersatile ultralow-power device options including:Masked ROMOTP (in-system programmable)Flash (in-system programmable)EPROM

Synchronous Operation13-413.3 Synchronous OperationIn USART synchronous mode, data and clock signals transmit and receiveserial data. The master suppl

Synchronous Operation13-5USART Peripheral Interface, SPI ModeFigure 13–3. MSP430 USART as Master, External Device With SPI as SlaveReceive Buffer URXB

Synchronous Operation13-6H) Second character is finished and sets the interrupt flag.I) Master receives 2Ah and slave receives 74h (right justified).F

Synchronous Operation13-7USART Peripheral Interface, SPI ModeFigure 13–6 illustrates the USART module functioning as a slave in a three orfour-pin SPI

Synchronous Operation13-813.3.1.1 Four-Pin SPI Master ModeThe signal on STE is used by the active master to prevent bus conflicts withanother master.

Interrupt and Control Functions13-9USART Peripheral Interface, SPI Mode13.4 Interrupt and Control FunctionsThe USART peripheral interface serves two m

Interrupt and Control Functions13-10Figure 13–7. State Diagram of Receiver Enable Operation—MSP430 as MasterIdle State(ReceiverEnabled)ReceiveDisableR

Interrupt and Control Functions13-11USART Peripheral Interface, SPI ModeFigure 13–9. State Diagram of Receive Enable—MSP430 as Slave, Four-Pin ModeIdl

Interrupt and Control Functions13-1213.4.2.2 Receive/Transmit Enable, MSP430 is SlaveFigure 13–11 shows the receive/transmit-enable-bit activity when

Interrupt and Control Functions13-13USART Peripheral Interface, SPI Mode13.4.3 USART Receive-Interrupt OperationIn the receive-interrupt operation sho

13x Devices1-41.4 13x DevicesThe 13x devices contain the following peripherals:Basic Clock System (on-chip DCO + one or two crystal oscillators)Watchd

Interrupt and Control Functions13-1413.4.4 Transmit-Interrupt OperationIn the transmit-interrupt operation shown in Figure 13–14, the transmit-interru

Control and Status Registers13-15USART Peripheral Interface, SPI Mode13.5 Control and Status RegistersThe USART registers, shown in Tables 13–2 and 13

Control and Status Registers13-1613.5.1 USART Control RegisterThe information stored in the control register, shown in Figure 13–15,determines the bas

Control and Status Registers13-17USART Peripheral Interface, SPI ModeBit 0: Master mode:The transmitter-empty flag TXEPT is set when the transmittersh

Control and Status Registers13-18Figure 13–17. USART Clock Phase and Polarity12345678**Cycle#UCLKUCLKUCLKUCLKSIMO/SOMISIMO/SOMIData toTXBUFReceiveSamp

Control and Status Registers13-19USART Peripheral Interface, SPI Modetransition signal to pin STE. FE is reset by a SWRST, a systemreset, by reading t

Control and Status Registers13-2013.5.6 Transmit Data Buffer UTXBUFThe transmit data buffer (UTXBUF), shown in Figure 13–22, contains currentdata for

14-1Comparator_A Comparator_AThe Comparator_A peripheral module is used to compare analog signals tosupport various forms of analog-to-digital convers

Comparator_A Overview14-214.1 Comparator_A OverviewThe primary function of the comparator module is to support precision A/Dslope-conversion applicati

Comparator_A Description14-3Comparator_A14.2 Comparator_A DescriptionThe comparator_A peripheral module is comprised of several major blocks.These blo

2-1Architectural Overview Architectural OverviewThis section describes the basic functions of an MSP430-based system.The MSP430 devices contain the fo

Comparator_A Description14-4A comparator output will oscillate if the voltage difference across the input ter-minals is small. Internal and external p

Comparator_A Description14-5Comparator_A14.2.6 Comparator_A Interrupt CircuitryOne interrupt and one interrupt vector are associated with the Comparat

Comparator_A Control Registers14-614.3 Comparator_A Control RegistersThe Comparator_A module is configured with three module registers asshown in Tabl

Comparator_A Control Registers14-7Comparator_ACARSEL, bit6:The internal reference VCAREF, selected by CAREF bits,is applied to the +terminal or –termi

Comparator_A Control Registers14-8The control bits CAPD.0 to CAPD.7 are initially reset, enabling all the inputbuffers for the associated port. The po

Comparator_A in Applications14-9Comparator_A14.4 Comparator_A in ApplicationsThe Comparator_A can be used to:Measure resistive elementsDetect external

Comparator_A in Applications14-10Figure 14–6. Application Example With One Active(Driving R3) and Three Passive PinsWith Applied Analog SignalsControl

Comparator_A in Applications14-11Comparator_A14.4.2 Comparator_A Used to Measure Resistive ElementsThe Comparator_A can be used to measure resistive e

Comparator_A in Applications14-12Figure 14–8. Timing for Temperature Measurement SystemsVCVCC0.25 × VCCPhase I:Charge-UpPhase II:Discharge CPhase III:

Comparator_A in Applications14-13Comparator_A14.4.3 Measuring Two Independent Resistive Element SystemsIt is possible to measure two independent syste

Introduction2-22.1 IntroductionThe architecture of the MSP430 family is based on a memory-to-memoryarchitecture, a common address space for all functi

Comparator_A in Applications14-14In Figure 14–10, the active signal paths are shown when the upper indepen-dent system is selected for conversion. Thi

Comparator_A in Applications14-15Comparator_AFigure 14–11 shows the active signal paths for the lower independent system.This example uses the 0.25×VC

Comparator_A in Applications14-1614.4.4 Comparator_A Used to Detect a Current or Voltage LevelComparator_A can be used to detect current or voltage le

Comparator_A in Applications14-17Comparator_AIn Figure 14–13 current is transferred to an input voltage by I × R(sense). Thecurrent limit is set for e

Comparator_A in Applications14-18Figure 14–14. Measuring a Current Source_+01CAFSetCAIFGτ ∼ 2 µs01010101CA0CA101P2CA0P2CA1VCAREFCARSEL02133 2 10CAREF0

Comparator_A in Applications14-19Comparator_AFigure 14–16. A/D Converter for Voltage Sources_+01CAFSetCAIFGτ ∼ 2 µs01010101CA0CA101P2CA0P2CA1VCAREFCAR

Comparator_A in Applications14-2014.4.6 Measuring the Offset Voltage of Comparator_AThe input offset voltage of the comparator varies with each device

Comparator_A in Applications14-21Comparator_AFigure 14–20. Measuring the Offset Voltage of the Comparator, CAEX = 1_+01CAFSetCAIFGτ ∼ 2 µs01010101CA0C

Comparator_A in Applications14-2214.4.7 Compensating for the Offset Voltage of Comparator_AAnother way to improve the accuracy is to compensate for th

Comparator_A in Applications14-23Comparator_AFigure 14–22 shows how to add hysteresis to the comparator to prevent outputoscillation.Figure 14–22. Use

Program Memory2-3Architectural Overview2.3 Program MemoryInstruction fetches from program memory are always 16-bit accesses,whereas data memory can be

14-24

15-1ADC12 ADC12The ADC12 12-bit analog-to-digital converter is a high-speed, extremely ver-satile analog-to-digital converter implemented on MSP430x13

Introduction15-215.1 IntroductionThe ADC12 12-bit analog-to-digital converter (shown in Figure 15–1) has fivemain functional blocks that can be indivi

Introduction15-3ADC12The ADC12 has versatile sample-and-hold circuitry giving the user manyoptions for control of the sample timing. The sample timing

ADC12 Description and Operation15-4Versatile conversion modes including single-channel, repeated single-channel, sequence, and repeated sequence.Sixte

ADC12 Description and Operation15-5ADC12Caution! ADC12 Turnon TimeWhen the ADC12 is turned on with the ADC12ON bit, the turnontime noted in the data s

Analog Inputs and Multiplexer15-6Warning ! Reference Voltage Settling TimeWhen the built-in reference is turned on with the VREFON bit, thesettling ti

Analog Inputs and Multiplexer15-7ADC1215.3.2 Input Signal ConsiderationsDuring sampling, the analog input signal is applied to the internal capacitora

Conversion Memory15-815.4 Conversion MemoryA typical approach in single-channel converters uses an interrupt request tosignal the end of the conversio

Conversion Modes15-9ADC1215.5 Conversion ModesThe ADC12 has four conversion modes:Single-channel, single-conversionSingle-channel, repeated-conversion

How to Use This Manualiii Read This FirstPrefaceRead This FirstAbout This ManualThe MSP430x1xx User’s Guide is intended to assist the development of

Peripherals2-42.6 PeripheralsPeripheral modules are connected to the CPU through the MAB, MDB, andinterrupt service and request lines. The MAB is usua

Conversion Modes15-10VR–) is configured in the same conversion-memory control register by the Srefbits. The conversion result is stored in conversion-

Conversion Modes15-11ADC12Figure 15–5. Single-Channel, Single-Conversion ModeADC12offx = CStartAddWait for EnableENC =Wait for TriggerSample, InputCh

Conversion Modes15-12Figure 15–6. Example Conversion-Memory SetupSelect0140h0142h015Ch015Eh12–bit S A RADC12MEM0ADC12MEM14ADC12MEM1516 x 12–bitADC Mem

Conversion Modes15-13ADC12no sample-and-conversion is active, or after an active sample-and-conversionis completed. The original sequence may not be c

Conversion Modes15-14An illustration of sequence of channels mode is shown in Figure 15–8.Figure 15–8. Sequence-of-Channels ModeADC12offx = CStartAddW

Conversion Modes15-15ADC12An example showing a sequence of conversions is shown and flow-chartedin Figures 15–9 and 15–10. The example shows the seque

Conversion Modes15-16Figure 15–10. Sequence-of-Channels Mode Example0140h0142h015Ch015Eh12–bit S A RADC12MEM0ADC12MEM14ADC12MEM1516 x 12–bitADC Memory

Conversion Modes15-17ADC12An illustration of repeat-single-channel mode is shown in Figure 15–11.Figure 15–11.Repeat-Single-Channel ModeADC12offx = CS

Conversion Modes15-18pletes, except when the new mode is repeat-single-channel. In this case, thesequence does not complete and the new mode takes eff

Conversion Modes15-19ADC12An illustration of repeat-sequence-of-channels mode is shown inFigure 15–12.Figure 15–12. Repeat-Sequence-of-Channels ModeAD

3-1System Resets, Interrupts, and Operating Modes System Resets, Interrupts,and Operating ModesThis chapter discusses the MSP430x1xx system resets, in

Conversion Modes15-20The intermediate modes are caused by the asynchronous clocks for the CPUand the ADC12. These intermediate modes can be avoided si

Conversion Clock and Conversion Speed15-21ADC12Caution! The following must be considered when turning theADC12 and voltage reference on or off. ADC12

Sampling15-22The conversion starts with the falling edge of the sample signal SAMPCON(see the Sampling section and Figure 15–14). Thirteen conversion

Sampling15-23ADC12Figure 15–15. Sample and Conversion, Basic Signal TimingSAMPCONSampleConversionand HoldStartSamplingStop SamplingStart ConversionSto

Sampling15-24To prevent this problem, synchronization logic is implemented in the sampleinput selection switch. This ensures that the first sample-and

Sampling15-25ADC12In pulse-sampling mode, sampling time is a multiple of the ADC12CLK x 4, andis calculated by:tsample = 4 x tADC12CLK x SHTxSHTx is d

Sampling15-26Figure 15–19. Pulse-Sample Mode Example TimingTimer_B.OUT0tsynctsampletconvertSAMPCONADC12CLKAdditional edges are ignored until after con

Sampling15-27ADC12Figure 15–21. Extended-Sample Mode Example ConfigurationACLKMCLKSMCLKADC12OSCInternalOscillatorADC12CLKS/HDivide by1,2,3,4,5,6,7,8Sa

Sampling15-28Figure 15–23. Use of MSC Bit With Nonrepeated ModesADC12CLKSAMPCONSamplingTimerSHPSHT0SHT1SAMPCONSHISHISingle channelENCMSC = 0MSC = 0Seq

Sampling15-29ADC1215.7.5 Sample Timing ConsiderationsThe A/D converter uses the charge redistribution method. Thus, when theinputs are internally swit

System Reset and Initialization3-23.1 System Reset and Initialization3.1.1 IntroductionThe MSP430 system reset circuitry (shown in Figure 3–1) sources

ADC12 Control Registers15-30and the time to charge to 1/2 LSB (minimum sampling time) is:tch(1/2 LSB) = Rt x Ci x In(8192)Where:In(8192) = 9.011Theref

ADC12 Control Registers15-31ADC1215.8.1 Control Registers ADC12CTL0 and ADC12CTL1All control bits of ADC12CTLx are reset during POR. Most of the contr

ADC12 Control Registers15-32ADC12TOVIE bit2 Conversion-time-overflow interrupt enable.The timing overflow happens if another sample-and-conversion isr

ADC12 Control Registers15-33ADC12SHT0 bits8–11Sample-and-hold Time0. These bits define the sample timing forconversions whose results are stored in co

ADC12 Control Registers15-34ADC12SSEL bits3–4Select the clock source for the converter core0: ADC12 internal oscillator, ADC12OSC1: ACLK2: MCLK3: SMCL

ADC12 Control Registers15-35ADC1215.8.2 Conversion-Memory Registers ADC12MEMxThere are sixteen conversion-memory registers ADC12MEMx as follows:0rw rw

ADC12 Control Registers15-36080h...08FhADC12MCTLx07rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0)EOSSref, source of referenceINCH, input chan

ADC12 Control Registers15-37ADC1215.8.4 ADC12 Interrupt Flags ADC12IFG.x and Interrupt-Enable RegistersADC12IEN.xThere are 16 ADC12IFG.x interrupt fla

ADC12 Control Registers15-38It is important to note that ADC12OVIFG and ADC12TOVIFG are reset auto-matically when either is the highest pending interr

ADC12 Control Registers15-39ADC1215.8.5.1 ADC Interrupt Vector Register, Software ExampleThe following software example shows the use of vector word A

System Reset and Initialization3-3System Resets, Interrupts, and Operating ModesNote:Generation of the POR/PUC signals does not necessarily generate a

ADC12 Control Registers15-40RETI ; Back to main program 5;ADC12MOD1 ; Vector 8: ADC12MEM1 was loaded; (ADC12IFG.1)ADD &ADC12MEM1,R6 ; ADC12IFG1 is

A/D Grounding and Noise Considerations15-41ADC1215.9 A/D Grounding and Noise ConsiderationsAs with any high-resolution converter, care and special att

15-42

A-1Peripheral File MapPeripheral File MapThis appendix summarizes the peripheral file (PF) and control-bit informationinto a single location for refe

OverviewA-2A.1 OverviewBit accessibility and/or hardware definitions are indicated following each bitsymbol:rw: Read/writer: Read onlyr0: Read as 0r1:

Special Function Register of MSP430x1xx Family, Byte AccessA-3Peripheral File MapA.2 Special Function Register of MSP430x1xx Family, Byte Access000FhM

Digital I/O, Byte Access (Continued)A-4A.3 Digital I/O, Byte Access (Continued)Bit # -76543210Function select, P6SEL0037hP6SEL.7rw-0P6SEL.6rw-0P6SEL.5

Basic Clock Registers, Byte AccessA-5Peripheral File MapA.4 Basic Clock Registers, Byte AccessBit # – 7 6 5 4 3 2 1 0BCSCTL20058hSELM.1rw–0SELM.0rw–

USART0, USART1, UART Mode (Sync=0), Byte AccessA-6A.7 USART0, USART1, UART Mode (Sync=0), Byte AccessBit # – 7 6 5 4 3 2 1 0USART1Transmit buffer UTXB

USART0, USART1, SPI Mode (Sync=1), Byte AccessA-7Peripheral File MapA.8 USART0, USART1, SPI Mode (Sync=1), Byte AccessBit # – 7 6 5 4 3 2 1 0USART1Tra

System Reset and Initialization3-43.1.2 Device Initialization After System ResetAfter a device reset (POR/PUC combination), the initial system conditi

ADC12 Registers, Byte and Word AccessA-8A.9 ADC12 Registers, Byte and Word AccessBit # –76543210ADC12MCTL15†008FhEOSrw–(0)Sref.2rw–(0)Sref.1rw–(0)Sr

ADC12 Registers, Byte and Word Access (Continued)A-9Peripheral File MapA.9 ADC12 Registers, Byte and Word Access (Continued)Bit # – 15 14 13 12 11

ADC12 Registers, Byte and Word Access (Continued)A-10A.9 ADC12 Registers, Byte and Word Access (Continued)Bit # –151413121110 9 8ADC12IE01A6hADC12IE

Watchdog/Timer, Word AccessA-11Peripheral File MapA.10 Watchdog/Timer, Word AccessBit # – 15 8Watchdog Timer, Control register WDTCTL120h <––––––

Hardware Multiplier, Word AccessA-12A.12 Hardware Multiplier, Word AccessBit # – 15 14 13 12 11 10 9 8Sum extend, SumExt013Eh†r†r†r†r†r†r†r†rResult-

Timer_A Registers, Word AccessA-13Peripheral File MapA.13 Timer_A Registers, Word AccessBit # – 15 14 13 12 11 10 9 8017Eh017ChCap/com register CC

Timer_A Registers, Word Access (Continued)A-14A.13 Timer_A Registers, Word Access (Continued)Bit # – 7 6 5 4 3 2 1 0017Eh017ChCap/com register CCR4

Timer_B Registers, Word AccessA-15Peripheral File MapA.14 Timer_B Registers, Word AccessBit # – 15 14 13 12 11 10 9 8Cap/com regis-ter CCR6†019Eh2

Timer_B Registers, Word Access (Continued)A-16A.14 Timer_B Registers, Word Access (Continued)Bit # – 7 6 5 4 3 2 1 0Cap/com register CCR6†019Eh27rw

Timer_B Registers, Word Access (Continued)A-17Peripheral File MapA.14 Timer_B Registers, Word Access (Continued)Bit # – 15 14 13 12 11 10 9 8Timer_

Global Interrupt Structure3-5System Resets, Interrupts, and Operating Modes3.2 Global Interrupt StructureThere are four types of interrupts:System res

A-18

B-1Instruction Set DescriptionInstruction Set DescriptionThe MSP430 core CPU architecture evolved from a reduced instruction setwith highly-transpare

Instruction Set OverviewB-2B.1 Instruction Set OverviewThe following list gives an overview of the instruction set.Status BitsVNZC* ADC[.W];ADC.B dst

Instruction Set OverviewB-3Instruction Set DescriptionStatus BitsVNZCMOV[.W];MOV.B src,dst src –> dst – – – –* NOP No operation – – – –* POP[.W];PO

Instruction Set OverviewB-4B.1.1 Instruction FormatsThe following sections describe the instruction formats.B.1.1.1 Double-Operand Instructions (Core

Instruction Set OverviewB-5Instruction Set DescriptionB.1.1.2 Single Operand Instructions (Core Instructions)The instruction format using a single ope

Instruction Set OverviewB-6JC/JHS Label Jump to label if carry bit is setJEQ/JZ Label Jump to label if zero bit is setJGE Label Jump to label if (N .X

Instruction Set OverviewB-7Instruction Set DescriptionThe following list describes the emulated instruction short form.Mnemonic Description Status Bit

Instruction Set OverviewB-8B.2 Instruction Set DescriptionThis section catalogues and describes all core and emulated instructions inalphabetical orde

Instruction Set OverviewB-9 Instruction Set DescriptionADC[.W] Add carry to destinationADC.B Add carry to destinationSyntax ADC dst or ADC.W

MSP430 Interrupt-Priority Scheme3-63.3 MSP430 Interrupt-Priority SchemeThe interrupt priority of the modules, as shown in Figure 3–4, is defined by th

Instruction Set OverviewB-10ADD[.W] Add source to destinationADD.B Add source to destinationSyntax ADD src,dst or ADD.W src,dstADD.B src,dstOperation

Instruction Set OverviewB-11 Instruction Set DescriptionADDC[.W] Add source and carry to destinationADDC.B Add source and carry to destinationSyntax

Instruction Set OverviewB-12AND[.W] Source AND destinationAND.B Source AND destinationSyntax AND src,dst or AND.W src,dstAND.B src,dstOperation src .A

Instruction Set OverviewB-13 Instruction Set DescriptionBIC[.W] Clear bits in destinationBIC.B Clear bits in destinationSyntax BIC src,dst or BIC.W s

Instruction Set OverviewB-14BIS[.W] Set bits in destinationBIS.B Set bits in destinationSyntax BIS src,dst or BIS.W src,dstBIS.B src,dstOperation src

Instruction Set OverviewB-15 Instruction Set DescriptionBIT[.W] Test bits in destinationBIT.B Test bits in destinationSyntax BIT src,dst or BIT.W src

Instruction Set OverviewB-16* BR, BRANCH Branch to ... destinationSyntax BR dstOperation dst –> PCEmulation MOV dst,PCDescription An uncondi

Instruction Set OverviewB-17 Instruction Set DescriptionCALL SubroutineSyntax CALL dstOperation dst –> tmp dst is evaluated and storedSP – 2

Instruction Set OverviewB-18* CLR[.W] Clear destination* CLR.B Clear destinationSyntax CLR dst or CLR.W dstCLR.B dstOperation 0 –> dstEmulation MOV

Instruction Set OverviewB-19 Instruction Set Description* CLRC Clear carry bitSyntax CLRCOperation 0 –> CEmulation BIC #1,SRDescription The carry

MSP430 Interrupt-Priority Scheme3-7System Resets, Interrupts, and Operating ModesFigure 3–5. Block Diagram of NMI Interrupt SourcesFlash ModuleFlash M

Instruction Set OverviewB-20* CLRN Clear negative bitSyntax CLRNOperation 0 → Nor(.NOT.src .AND. dst –> dst)Emulation BIC #4,SRDescription The con

Instruction Set OverviewB-21 Instruction Set Description* CLRZ Clear zero bitSyntax CLRZOperation 0 → Zor(.NOT.src .AND. dst –> dst)Emulation BIC

Instruction Set OverviewB-22CMP[.W] Compare source and destinationCMP.B Compare source and destinationSyntax CMP src,dst or CMP.W src,dstCMP.B src,d

Instruction Set OverviewB-23 Instruction Set Description* DADC[.W] Add carry decimally to destination* DADC.B Add carry decimally to destinationSynta

Instruction Set OverviewB-24DADD[.W] Source and carry added decimally to destinationDADD.B Source and carry added decimally to destinationSyntax DADD

Instruction Set OverviewB-25 Instruction Set Description* DEC[.W] Decrement destination* DEC.B Decrement destinationSyntax DEC dst or DEC.W dstDEC.

Instruction Set OverviewB-26Example R10 is decremented by 1DEC R10 ; Decrement R10; Move a block of 255 bytes from memory location starting with EDE t

Instruction Set OverviewB-27 Instruction Set Description* DECD[.W] Double-decrement destination* DECD.B Double-decrement destinationSyntax DECD dst

Instruction Set OverviewB-28* DINT Disable (general) interruptsSyntax DINTOperation 0 → GIEor(0FFF7h .AND. SR → SR / .NOT.src .AND. dst –> dst)Emul

Instruction Set OverviewB-29 Instruction Set Description* EINT Enable (general) interruptsSyntax EINTOperation 1 → GIEor(0008h .OR. SR –> SR / .

MSP430 Interrupt-Priority Scheme3-8Figure 3–6. RST/NMI Mode SelectionNMIESHOLD NMI TMSEL CNTCL SSEL IS1 IS0WDTCTL0120hrw-0 rw-0 rw-0 rw-0 (w)-0 rw-0 r

Instruction Set OverviewB-30* INC[.W] Increment destination* INC.B Increment destinationSyntax INC dst or INC.W dstINC.B dstOperation dst + 1 –> ds

Instruction Set OverviewB-31 Instruction Set Description* INCD[.W] Double-increment destination* INCD.B Double-increment destinationSyntax INCD dst o

Instruction Set OverviewB-32* INV[.W] Invert destination* INV.B Invert destinationSyntax INV dstINV.B dstOperation .NOT.dst –> dstEmulation XOR #0F

Instruction Set OverviewB-33 Instruction Set DescriptionJC Jump if carry setJHS Jump if higher or sameSyntax JC labelJHS labelOperation If C = 1: PC

Instruction Set OverviewB-34JEQ, JZ Jump if equal, jump if zeroSyntax JEQ label, JZ labelOperation If Z = 1: PC + 2 × offset –> PCIf Z = 0: execut

Instruction Set OverviewB-35 Instruction Set DescriptionJGE Jump if greater or equalSyntax JGE labelOperation If (N .XOR. V) = 0 then jump to label:

Instruction Set OverviewB-36JL Jump if lessSyntax JL labelOperation If (N .XOR. V) = 1 then jump to label: PC + 2 × offset –> PCIf (N .XOR. V) = 0

Instruction Set OverviewB-37 Instruction Set DescriptionJMP Jump unconditionallySyntax MP labelOperation PC + 2 × offset –> PCDescription The 10-

Instruction Set OverviewB-38JN Jump if negativeSyntax JN labelOperation if N = 1: PC + 2 × offset –> PCif N = 0: execute following instructionDesc

Instruction Set OverviewB-39 Instruction Set DescriptionJNC Jump if carry not setJLO Jump if lowerSyntax JNC labelJNC labelOperation if C = 0: PC + 2

Interrupt Processing3-9System Resets, Interrupts, and Operating Modes3.3.2 Operation of Global Interrupt—Oscillator Fault ControlThe oscillator fault

Instruction Set OverviewB-40JNE, JNZ Jump if not equal, jump if not zeroSyntax JNE label, JNZ labelOperation If Z = 0: PC + 2 × offset –> PCIf Z =

Instruction Set OverviewB-41 Instruction Set DescriptionMOV[.W] Move source to destinationMOV.B Move source to destinationSyntax MOV src,dst or

Instruction Set OverviewB-42* NOP No operationSyntax NOPOperation NoneEmulation MOV #0,#0Description No operation is performed. The instruction may b

Instruction Set OverviewB-43 Instruction Set Description* POP[.W] Pop word from stack to destination* POP.B Pop byte from stack to destinationSynta

Instruction Set OverviewB-44PUSH[.W] Push word onto stackPUSH.B Push byte onto stackSyntax PUSH src or PUSH.W srcPUSH.B srcOperation SP

Instruction Set OverviewB-45 Instruction Set Description* RET Return from subroutineSyntax RETOperation @SP→ PCSP + 2 → SPEmulation MOV @SP+,PCDescri

Instruction Set OverviewB-46RETI Return from interruptSyntax RETIOperation TOS → SRSP + 2 → SPTOS → PCSP + 2 → SPDescription The status register is r

Instruction Set OverviewB-47 Instruction Set Description* RLA[.W] Rotate left arithmetically* RLA.B Rotate left arithmeticallySyntax RLA dst or RLA.

Instruction Set OverviewB-48* RLC[.W] Rotate left through carry* RLC.B Rotate left through carrySyntax RLC dst or RLC.W dstRLC.B dstOperation C <–

Instruction Set OverviewB-49 Instruction Set DescriptionRRA[.W] Rotate right arithmeticallyRRA.B Rotate right arithmeticallySyntax RRA dst or RRA.W d

Related Documentation From Texas InstrumentsivChapter 14 – Comparator_AChapter 15 – ADC12Appendix A – Peripheral File MapAppendix B – Instruction Set

Interrupt Processing3-108) The content of the appropriate interrupt vector is loaded into the programcounter: the program continues with the interrupt

Running Title—Attribute ReferenceB-50Example R5 is shifted right one position. The MSB retains the old value. It operatesequal to an arithmetic divisi

Instruction Set OverviewB-51 Instruction Set DescriptionRRC[.W] Rotate right through carryRRC.B Rotate right through carrySyntax RRC dst or RRC.W dst

Instruction Set OverviewB-52* SBC[.W] Subtract (borrow*) from destination* SBC.B Subtract (borrow*) from destinationSyntax SBC dst or SBC.W dstSBC.B d

Instruction Set OverviewB-53 Instruction Set Description* SETC Set carry bitSyntax SETCOperation 1 –> CEmulation BIS #1,SRDescription The carry b

Instruction Set OverviewB-54* SETN Set negative bitSyntax SETNOperation 1 –> NEmulation BIS #4,SRDescription The negative bit (N) is set.Status Bi

Instruction Set OverviewB-55 Instruction Set Description* SETZ Set zero bitSyntax SETZOperation 1 –> ZEmulation BIS #2,SRDescription The zero bit

Instruction Set OverviewB-56SUB[.W] Subtract source from destinationSUB.B Subtract source from destinationSyntax SUB src,dst or SUB.W src,dstSUB.B sr

Instruction Set OverviewB-57 Instruction Set DescriptionSUBC[.W]SBB[.W] Subtract source and borrow/.NOT. carry from destinationSUBC.B,SBB.B Subtra

Instruction Set OverviewB-58SWPB Swap bytesSyntax SWPB dstOperation Bits 15 to 8 <–> bits 7 to 0Description The destination operand high and low

Instruction Set OverviewB-59 Instruction Set DescriptionSXT Extend SignSyntax SXT dstOperation Bit 7 –> Bit 8 ... Bit 15Description The sign

Interrupt Processing3-11System Resets, Interrupts, and Operating ModesFigure 3–9. Status Register (SR)SCG0 GIE Z Crw-015 0Reserved For Future Enhancem

Instruction Set OverviewB-60* TST[.W] Test destination* TST.B Test destinationSyntax TST dst or TST.W dstTST.B dstOperation dst + 0FFFFh + 1dst + 0FFh

Instruction Set OverviewB-61 Instruction Set DescriptionXOR[.W] Exclusive OR of source with destinationXOR.B Exclusive OR of source with destinationS

B-62

C-1Flash MemoryFlash MemoryThis chapter describes the MSP430 flash memory module. The flash memorymodule is electrically erasable and programmable. De

Flash Memory OrganizationC-2C.1 Flash Memory OrganizationThe flash memory may have one or more modules of different sizes as shownin Figure C–1. A mod

Flash Memory OrganizationC-3Flash Memorybus and memory data bus. When a second module (here Module2) isimplemented, program code in this module can be

Flash Memory OrganizationC-4Figure C–3.Flash Memory Module ExampleFFFFh Flash MemoryF000h010FFh01000h 4Kbyte + 256Byte ONE module4-kbyteFlashMemory256

Flash Memory Data Structure and OperationC-5Flash MemoryFigure C–4.Segments in Flash Memory Module, 4K-Byte ExampleFFFFh Flash MemoryF000h010FFh01000h

Flash Memory Data Structure and OperationC-6C.2.1 Flash Memory Basic FunctionsThe basic functions of flash memory are to:Supply program code and data

Flash Memory Data Structure and OperationC-7Flash Memoryor erase operation. Once these registers are set up and write or erase isstarted, the timing g

Interrupt Processing3-12Table 3–2.Interrupt Enable Registers 1 and 2Bit Position Short Form Initial State†CommentsIE1.0 WDTIE Reset Watchdog timer ena

Flash Memory Data Structure and OperationC-8Table C–1. Control Bits for Write or Erase OperationFUNCTION PERFORMEDSEGWRT WRT Meras Erase BUSY WAIT Loc

Flash Memory Data Structure and OperationC-9Flash MemoryThe dummy write starts the erase cycle. An example of dummy write isCLR &0F012h.Note that

Flash Memory Data Structure and OperationC-10Note:When the erase cycle is stopped before its normal completion by the hard-ware, the timing generator

Flash Memory Data Structure and OperationC-11Flash MemoryFigure C–8.Basic Flash Memory Module Timing During Write (Single Byte or Word) CycleBUSYGener

Flash Memory Data Structure and OperationC-12The write cycle is successfully completed if none of the following restrictionsis violated:The selected c

Flash Memory Control RegistersC-13Flash MemoryThe supply voltage should be within the devices’ electrical conditions andcan only vary slightly, as spe

Flash Memory Control RegistersC-14ment write mode, the control register can be written if wait mode is active(WAIT=1). In an active segment write mode

Flash Memory Control RegistersC-15Flash MemoryC.3.2 Flash Memory Control Register FCTL2A PUC resets the flash timing generator. The generator is also

Flash Memory Control RegistersC-16C.3.3 Flash Memory Control Register FCTL3There are no restrictions on modifying this control register. The control b

Flash Memory Control RegistersC-17Flash MemoryACCVIFG bit2, Access violation interrupt flagThe access-violation interrupt flag is set when the flash m

Interrupt Processing3-13System Resets, Interrupts, and Operating ModesTable 3–3.Interrupt Flag Register 1 and 2Bit Position Short Form Initial State C

Flash Memory, Interrupt and Security Key ViolationC-18EMEX 012Ch, bit5, Emergency exit. The emergency exit should only be used when a flashmemory writ

Flash Memory, Interrupt and Security Key ViolationC-19Flash MemoryFigure C–10. Basic Flash Memory Module Timing During Segment Write CycleClearSPORRST

Flash Memory, Interrupt and Security Key ViolationC-20C.4.1 Example of an NMI Interrupt HandleryesnoOFIFG=1yesnoACCVIFG=1yesReset ACCVIFGnoNMIIFG=1Res

Flash Memory, Interrupt and Security Key ViolationC-21Flash MemoryTo protect the software from this error situation, all interrupt sources have tobe d

Flash Memory Access via JTAG and SoftwareC-22C.5 Flash Memory Access via JTAG and SoftwareC.5.1 Flash Memory ProtectionFlash memory access via the ser

Flash Memory Access via JTAG and SoftwareC-23Flash MemoryC.5.3.1 Example: Programming One Word Into a Flash Memory Module via SoftwareExecution Outsid

Flash Memory Access via JTAG and SoftwareC-24C.5.3.2 Example: Programming One Word Into the Same Flash Memory Module via SoftwareThe program execution

Flash Memory Access via JTAG and SoftwareC-25Flash MemoryC.5.3.3 Example, Programming Byte Sequences Into a Flash Memory Module via SoftwareSequences

Flash Memory Access via JTAG and SoftwareC-26C.5.3.4 Example, Erase Flash Memory Segment or Module via Software ExecutionOutside This Flash ModuleThe

Flash Memory Access via JTAG and SoftwareC-27Flash MemoryThe target flash memory module can not execute the programming code se-quence while data is b

Interrupt Processing3-14Table 3–4.Module Enable Registers 1 and 2Bit Position Short Form Initial State CommentsME1.0 ReservedME1.1 ReservedME1.2 Reser

C-28

Interrupt Processing3-15System Resets, Interrupts, and Operating Modes3.4.2 Interrupt Vector AddressesThe interrupt vectors and the power-up starting

Operating Modes3-163.5 Operating ModesThe MSP430 family was developed for ultralow-power applications and usesdifferent levels of operating modes. The

Operating Modes3-17System Resets, Interrupts, and Operating ModesReturn from interruptTwo different modes are available to return from the interrupt s

Operating Modes3-18Low power mode 2 (LPM2); SCG1=1, SCG0=0, OscOff=0, CPUOff=1:CPU is disabledMCLK is disabledSMCLK is disabledDCO oscillator automati

Operating Modes3-19System Resets, Interrupts, and Operating ModesTable 3–6.Low Power Mode Logic Chart for Basic Clock SystemSCG1 SCG0 OscOff CPUOffLPM

Running Title—Attribute Referencev Chapter Title—Attribute ReferenceContents1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Modes3-20Figure 3–11. Typical Current Consumption of 13x and 14x Devices vs. Operating Modes315AM34027022518013590450LPM0 LPM2 LPM3 LPM42257

Operating Modes3-21System Resets, Interrupts, and Operating ModesThe following example describes clearing low-power mode 0.;===Interrupt service routi

Basic Hints for Low-Power Applications3-223.6 Basic Hints for Low-Power ApplicationsThere are some basic practices to follow when current consumption

4-1Memory MemoryMSP430 devices are configured as a von-Neumann architecture. It has codememory, data memory, and peripherals in one address space. As

Introduction4-24.1 IntroductionAll of the physically separated memory areas (ROM, RAM, SFRs, andperipheral modules) are mapped into the common address

Data in the Memory4-3Memory4.2 Data in the MemoryBytes are located at even or odd addresses as shown in Figure 4–3. However,words are only located at

Internal ROM Organization4-44.3 Internal ROM OrganizationVarious sizes of ROM (OTP, masked-ROM, EPROM, or FLASH) are availablewithin the 64-kB address

Internal ROM Organization4-5Memory4.3.2 Computed Branches and CallsComputed branches and subroutine calls are possible using standardinstructions. The

RAM and Peripheral Organization4-64.4 RAM and Peripheral OrganizationThe entire RAM can be accessed with byte or word instructions using theappropriat

RAM and Peripheral Organization4-7MemoryIn the following examples, word-to-word and byte-to-byte operations show theresults of the operation and the s

Contentsvi4.4 RAM and Peripheral Organization 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Random

RAM and Peripheral Organization4-8Note: Word-Byte OperationsWord-byte or byte-word operations on memory data are not supported. Eachregister-byte or b

RAM and Peripheral Organization4-9MemoryTable 4–1.Peripheral File Address Map—Word ModulesAddress Description1F0h – 1FFh Reserved1E0h – 1EFh Reserved1

RAM and Peripheral Organization4-10Table 4–2.Peripheral File Address Map—Byte ModulesAddress Description00F0h – 00FFh Reserved00E0h – 00EFh Reserved00

RAM and Peripheral Organization4-11MemoryTable 4–3.Special Function Register Address MapAddress Data Bus70000Fh Not yet defined or implemented000Eh No

4-12

5-116-Bit CPU 16-Bit CPUThe MSP430 von-Neumann architecture has RAM, ROM, and peripherals inone address space, both using a single address and data bu

CPU Registers5-25.1 CPU RegistersSixteen 16-bit registers (R0, R1, and R4 to R15) are used for data andaddresses and are implemented in the CPU. They

CPU Registers5-316-Bit CPU5.1.2.1 Examples for System SP Addressing (Refer to Figure 5–4)MOV SP,R4 ; SP –> R4MOV @SP,R5 ; Item I3 (TOS) –> R5MOV

CPU Registers5-45.1.3 The Status Register (SR)The status register SR contains the following CPU status bits:V Overflow bitSCG1 System clock generator

CPU Registers5-516-Bit CPU Note: Status Register Bits V, N, Z, and CThe status register bits V, N, Z, and C are modified only with the appropriateinst

Contentsvii Contents7.4 Basic Clock Module Operating Modes 7-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1

CPU Registers5-6The RISC instruction set of the MSP430 only has 27 instructions. However, theconstant generator allows the MSP430 assembler to support

Addressing Modes5-716-Bit CPU5.2 Addressing ModesAll seven addressing modes for the source operand and all four addressingmodes for the destination op

Addressing Modes5-85.2.1 Register ModeThe register mode is described in Table 5–5.Table 5–5.Register Mode DescriptionAssembler Code Content of ROMMOV

Addressing Modes5-916-Bit CPU5.2.2 Indexed ModeThe indexed mode is described in Table 5–6.Table 5–6.Indexed Mode DescriptionAssembler Code Content of

Addressing Modes5-105.2.3 Symbolic ModeThe symbolic mode is described in Table 5–7.Table 5–7.Symbolic Mode DescriptionAssembler Code Content of ROMMOV

Addressing Modes5-1116-Bit CPU5.2.4 Absolute ModeThe absolute mode is described in Table 5–8.Table 5–8.Absolute Mode DescriptionAssembler Code Content

Addressing Modes5-125.2.5 Indirect ModeThe indirect mode is described in table 5–9.Table 5–9.Indirect Mode DescriptionAssembler Code Content of ROMMOV

Addressing Modes5-1316-Bit CPU5.2.6 Indirect Autoincrement ModeThe indirect autoincrement mode is described in Table 5–10.Table 5–10.Indirect Autoincr

Addressing Modes5-145.2.7 Immediate ModeThe immediate mode is described in Table 5–11.Table 5–11. Immediate Mode DescriptionAssembler Code Content of

Addressing Modes5-1516-Bit CPU5.2.8 Clock Cycles, Length of InstructionThe operating speed of the CPU depends on the instruction format andaddressing

Contentsviii11 Timer_B 11-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Addressing Modes5-165.2.8.2 Format-II InstructionsTable 5–13 describes the CPU format II instructions and addressing modes.Table 5–13.Instruction Form

Instruction Set Overview5-1716-Bit CPU5.3 Instruction Set OverviewThis section gives a short overview of the instruction set. The addressingmodes are

Instruction Set Overview5-185.3.1 Double-Operand InstructionsFigure 5–7 illustrates the double-operand instruction format.Figure 5–7. Double Operand I

Instruction Set Overview5-1916-Bit CPU5.3.2 Single-Operand InstructionsFigure 5–8 illustrates the single-operand instruction format.Figure 5–8. Single

Instruction Set Overview5-205.3.3 Conditional JumpsConditional jumps support program branching relative to the program counter.The possible jump range

Instruction Set Overview5-2116-Bit CPU5.3.4 Short Form of Emulated InstructionsThe basic instruction set, together with the register implementations o

Instruction Set Overview5-22Table 5–18. Emulated Instructions (Continued)Mnemonic Description Status Bits EmulationV N Z CData Instructions (common us

Instruction Map5-2316-Bit CPU5.4 Instruction MapThe instruction map in Figure 5–10 is an example of how to encodeinstructions. There is room for more

5-24

6-1Hardware Multiplier Hardware MultiplierThe hardware multiplier is a 16-bit peripheral module. It is not integrated intothe CPU. Therefore, it requi

Contentsix Contents12.7 Baud Rate Considerations 12-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Multiplier Module Support6-26.1 Hardware Multiplier Module SupportThe hardware multiplier module expands the capabilities of the MSP430family

Hardware Multiplier Operation6-3Hardware Multiplier6.2 Hardware Multiplier OperationThe hardware multiplier has two 16-bit registers for both operands

Hardware Multiplier Operation6-4The sum extension register contents differ, depending on the operation andon the results of the operation.Table 6–1.Su

Hardware Multiplier Operation6-5Hardware Multiplier6.2.1 Multiply Unsigned, 16×16 bit, 16× 8 bit, 8× 16 bit, 8 × 8 bitThe following multiplication ope

Hardware Multiplier Operation6-66.2.2 Multiply Signed, 16×16 bit, 16×8 bit, 8×16 bit, 8×8 bitThe following multiplication operation shows 36 bytes of

Hardware Multiplier Operation6-7Hardware Multiplier6.2.3 Multiply Unsigned and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bitThe following multiplicat

Hardware Multiplier Operation6-86.2.4 Multiply Signed and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit**********************************************

Hardware Multiplier Registers6-9Hardware Multiplier6.3 Hardware Multiplier RegistersHardware multiplier registers are word structured, but can be acce

Hardware Multiplier Special Function Bits6-106.4 Hardware Multiplier Special Function BitsBecause the hardware multiplier module completes all multipl

Hardware Multiplier Software Restrictions6-11Hardware Multiplier6.5.2 Hardware Multiplier Software Restrictions—Interrupt RoutinesThe entire multiplic