Texas Instruments MSP50C614 manuals

MSP50C614

1

Mixed-Signal Processor

1

User’s Guide

1

Read This First

3

Notational Conventions

4

Trademarks

5

Contents

10

Notes, Cautions, and Warnings

16

Introduction to the MSP50C614

17

1.1 Features of the C614

18

1.2 Applications

19

Development Device: MSP50P614

20

1.4 Functional Description

21

Figure 1–3. RESET Circuit

25

Comparator

26

Scan Port Bond Out

26

Application Circuits

26

MSP50C614 Architecture

31

2.1 Architecture Overview

32

2.2 Computation Unit

35

Computation Unit

36

2.2.2 Arithmetic Logic Unit

37

Multiplier

38

2.2.2.1 Accumulator Block

38

Instructions

40

2.2.2.3 String Operations

40

2.3 Data Memory Address Unit

41

2.3.1 RAM Configuration

42

2.4 Program Counter Unit

44

2.5 Bit Logic Unit

44

2.6.1 Memory Map

45

2.6.3 Interrupt Vectors

48

2.6.4 ROM Code Security

49

2.7 Interrupt Logic

52

Internal and

53

External Interrupts

53

Interrupt Logic

54

2.8 Timer Registers

56

Speed Control Register

57

Clock Control

57

Timer Registers

58

2.9 Clock Control

59

Figure 2–9. PLL Performance

60

2.10 Execution Timing

63

2.11 Reduced Power Modes

64

Clock Speed Control Register

65

Reduced Power Modes

67

Table 2–4)

69

Interrupt Vectors

70

Peripheral Functions

71

Branch on D Port

73

3.1.2 Dedicated Input Port F

74

3.1.3 Dedicated Output Port G

75

3.1.4 Branch on D Port

76

Table 3–1. Interrupts

77

C3x style

79

Figure 3–1. PDM Clock Divider

80

3.3 Comparator

84

Dedicated Input

88

PDM Clock Divider

88

Chapter 4

93

4.1 Introduction

94

4.2 System Registers

94

4.2.5 Top of Stack, (TOS)

95

4.2.8 Accumulators (AC0–AC31)

96

System Registers

97

4.2.11 String Register (STR)

98

4.2.12 Status Register (STAT)

98

4.3.2 Addressing Modes

101

Table 4–3. Rx Bit Description

102

= 0x2f

104

= 0x12ef

104

4.3.3 Immediate Addressing

105

4.3.4 Direct Addressing

106

4.3.5 Indirect Addressing

107

4.3.6 Relative Addressing

108

4.3.7 Flag Addressing

111

4.3.8 Tag/Flag Bits

112

Table 4–11

115

Instruction Classification

117

Hardware Loop Instructions

145

4.8 String Instructions

147

String Instructions

148

4.9 Lookup Instructions

149

Lookup Instructions

150

Special Filter Instructions

152

Wrap around

155

FIRK_COEFFS

158

N+1 Taps

159

4.12 Conditionals

161

4.13 Legend

162

4.14.1 ADD Add word

167

4.14.2 ADDB ADD BYTE

169

4.14.3 ADDS Add String

170

4.14.4 AND Bitwise AND

172

4.14.5 ANDB Bitwise AND Byte

174

4.14.7 BEGLOOP Begin Loop

176

4.14.9 C

178

Conditional Subroutine Call

178

Table 4–48. Names for cc

179

4.14.10 CMP Compare Two Words

182

Example 4.14.10.4 CMP R0, R5

183

4.14.15 ENDLOOP End Loop

188

MOV AP0, 0

190

See Also RPT, FIRK, COR, CORK

193

Example 4.14.18.1 RPT 0

193

FIR A0, *R0

193

4.14.20 IDLE Halt Processor

195

4.14.24 INTE Interrupt Enable

199

4.14.26 J

201

Conditional Jumps

201

Description Copy value of

209

NOTE: B = Byte move possible

223

S = String move possible

223

R5 can be moved to Rx

223

4.14.48 NOP No Operation

234

4.14.51 OR Bitwise Logical OR

237

4.14.52 ORB Bitwise OR Byte

239

4.14.53 ORS Bitwise OR String

240

4.14.54 OUT Output to Port

241

{flagadrs}

244

4.14.61 RTAG Reset Tag

248

4.14.63 SFLAG Set Memory Flag

250

4.14.65 SHL Shift Left

252

4.14.78 STAG Set Tag

265

4.14.79 SUB Subtract

266

4.14.80 SUBB Subtract Byte

268

4.14.83 VCALL Vectored Call

272

4.14.84 XOR Logical XOR

273

4.14.85 XORB Logical XOR Byte

275

4.14.87 ZAC Zero Accumulator

277

A1~ to zero

278

4.15 Instruction Set Encoding

279

Instruction Set Encoding

280

4.16 Instruction Set Summary

288

Flagadrs

291

Instruction Set Summay

296

Code Development Tools

301

5.1 Introduction

302

5.3 Requirements

304

5.4 Hardware Installation

305

5.5 Software Installation

306

Figure 5–5. Setup Window

307

Figure 5–6. Exit Setup Dialog

308

Software Installation

309

Select Program Folder

310

Next >

310

Figure 5–10. Copying Files

311

Setup Complete

312

5.6 Software Emulator

313

Figure 5–13. Project Menu

314

5.6.2 Projects

315

5.6.3 Description of Windows

316

Figure 5–17. RAM Window

317

Figure 5–18. CPU Window

318

Figure 5–19. Program Window

319

Software Emulator

320

Figure 5–21. Inspect Dialog

321

Figure 5–22. Inspect Window

321

Figure 5–23. I/O Ports Window

322

Figure 5–24. Debug Menu

323

Figure 5–26. Trace Mode

326

Figure 5–27. Init Menu Option

327

5.6.6 Emulator Options

328

Figure 5–28. Options Menu

329

5.7 Assembler

333

5.7.2 Assembler Directives

334

SYM1 EQU (12 * 256)

335

SYM2 EQU SYM1 * (32 / 4)

335

SYM3 EQU SYM1 * SYM2 – *0x200

335

Users should NEVER

336

Assembler

337

5.8 Linker

338

5.9 C– – Compiler

339

5.9.1 Foreword

340

5.9.2 Variable Types

341

5.9.3 External References

341

5.9.4 C– – Directives

342

C– – Compiler

343

5.9.5 Include Files

344

5.9.7 Initializations

345

5.9.8 RAM Usage

345

5.9.9 Variable Types

345

5.9.10 String Functions

345

Table 5–1. String Functions

346

5.9.11 Constant Functions

347

5.10 Implementation Details

348

Implementation Details

349

5.10.2 Division

350

5.10.3 Function Calls

350

5.10.4 Programming Example

351

C to ASM function return

359

Beware of Stack Corruption

367

Applications

369

6.1 Application Circuits

370

6.2.1 File init.asm

373

Project – New Project

376

Project – Build

376

Debug – Eprom Programming

376

Blank Check + Program

376

Init – Init All

376

Extra, extra etc

377

6.3.1 Memory Overlay

381

Customer Information

383

7.1 Mechanical Information

384

7.1.2 Package Information

385

Mechanical Information

386

7.3 Speech Development Cycle

390

Device Production Sequence

391

7.5 Ordering Information

392

7.6 New Product Release Forms

392

New Product Release Forms

393

MSP50C605 Preliminary Data

395

A.1 Introduction

396

A.2 Features

396

A.3 Architecture

396

A.3.1 RAM

397

A.3.2 ROM

397

A.3.3 I/O Pins

397

Architecture

398

Data Memory

399

229,376 x 8 bit

399

Data ROM

399

MSP50C605 100 PIN PJM

400

PLASTIC PACKAGE

400

MSP50C604 Preliminary Data

403

B.1 Introduction

404

B.2 Features

404

B.3 Architecture

404

B.3.1 RAM

405

B.3.2 ROM

405

B.3.3 I/O Pins

405

B.3.4 Slave Mode Operation

407

B.3.5 Host Write Sequence

407

B.3.6 Host Read Sequence

407

RESET vector

408

B.3.7 Interrupts

409

B.4 Packaging

410

MSP50C604 64 PIN PJM

411

Packaging

412

MSP50C605 Data Sheet

413

C.1 MSP50C605 Data Sheet

414

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Texas Instruments MSP50C614 manuals

Texas instruments MSP50C614 User Manual (414 pages)

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