Texas Instruments PCI7421 User Manual

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xSection Title Page12.16 Slot Information Register 12−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.17 Capability ID and

4−104.15 PCI Bus Number RegisterThe PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to whichthe PCI

4−114.18 CardBus Latency Timer RegisterThe CardBus latency timer register is programmed by the host system to specify the latency timer for thePCI7x21

4−124.20 CardBus Memory Limit Registers 0, 1These registers indicate the upper address of a PCI memory address range. They are used by the PCI7x21/PCI

4−134.22 CardBus I/O Limit Registers 0, 1These registers indicate the upper address of a PCI I/O address range. They are used by the PCI7x21/PCI7x11co

4−144.24 Interrupt Pin RegisterThe value read from this register is function dependent. The default value for function 0 is 01h (INTA), the default va

4−15Register: Interrupt pinOffset: 3DhType: Read-onlyDefault: 01h (function 0), 02h (function 1), 03h (function 2), 04h (function 3), 04h (function 4

4−16Table 4−7. Bridge Control Register Description (Continued)BITSIGNAL TYPE FUNCTION6 † CRST RWCardBus reset. When this bit is set, the CRST signal i

4−174.27 Subsystem ID RegisterThe subsystem ID register, used for system and option card identification purposes, may be required for certainoperating

4−184.29 System Control RegisterSystem-level initializations are performed through programming this doubleword register. Some of the bits are globalin

4−19Table 4−8. System Control Register Description (continued)BIT SIGNAL TYPE FUNCTION22 ‡ CBRSVD RWCardBus reserved terminals signaling. When this bi

xiSection Title Page14 Electrical Characteristics 14−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Absolut

4−20Table 4−8. System Control Register Description (continued)BIT SIGNAL TYPE FUNCTION4 ‡§ CB_DPAR RWCardBus data parity SERR signaling enable.0 = Car

4−214.31 General Control RegisterThe general control register provides top level PCI arbitration control. It also provides the ability to disable the

4−22Table 4−9. General Control Register DescriptionBIT SIGNAL TYPE FUNCTION15 ‡FM_PWR_CTRL_POLRWFlash media power control pin polarity. This bit contr

4−234.32 General-Purpose Event Status RegisterThe general-purpose event status register contains status bits that are set when general events occur, a

4−244.33 General-Purpose Event Enable RegisterThe general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−

4−254.35 General-Purpose Output RegisterThe general-purpose output register is used to drive the GPO4−GPO0 outputs. See Table 4−13 for a completedescr

4−264.36 Multifunction Routing Status RegisterThe multifunction routing status register is used to configure the MFUNC6−MFUNC0 terminals. These termin

4−27Table 4−14. Multifunction Routing Status Register Description (Continued)BIT SIGNAL TYPE FUNCTION7−4 ‡ MFUNC1 RWMultifunction terminal 1 configura

4−284.38 Card Control RegisterThe card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and theenable

4−294.39 Device Control RegisterThe device control register is provided for PCI1130 compatibility. It contains bits that are shared between functions0

xiiList of IllustrationsFigure Title Page2−1 PCI7621 GHK/ZHK-Package Terminal Diagram 2−1. . . . . . . . . . . . . . . . . . . . . 2−2 PCI7421 GHK/ZHK

4−304.40 Diagnostic RegisterThe diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be writte

4−314.41 Capability ID RegisterThe capability ID register identifies the linked list item as the register for PCI power management. The register retur

4−324.43 Power Management Capabilities RegisterThe power management capabilities register contains information on the capabilities of the PC Card func

4−334.44 Power Management Control/Status RegisterThe power management control/status register determines and changes the current power state of thePCI

4−344.45 Power Management Control/Status Bridge Support Extensions RegisterThis register supports PCI bridge-specific functionality. It is required fo

4−354.47 Serial Bus Data RegisterThe serial bus data register is for programmable serial bus byte reads and writes. This register represents the dataw

4−364.49 Serial Bus Slave Address RegisterThe serial bus slave address register is for programmable serial bus byte read and write transactions. To wr

4−374.50 Serial Bus Control/Status RegisterThe serial bus control and status register communicates serial bus status information and selects the quick

4−38

5−15 ExCA Compatibility Registers (Functions 0 and 1)The ExCA (exchangeable card architecture) registers implemented in the PCI7x21/PCI7x11 controller

xiiiList of TablesTable Title Page1−1 Terms and Definitions 1−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5−216-Bit Legacy-Mode Base AddressPCI7x21/PCI7x11 Configuration Registers10hCardBus Socket/ExCA Base AddressNote: The 16-bit legacy-mode base addressr

5−3Table 5−1. ExCA Registers and OffsetsEXCA REGISTER NAMEPCI MEMORY ADDRESSOFFSET (HEX)EXCA OFFSET(CARD A)EXCA OFFSET(CARD B)Identification and revis

5−4Table 5−1. ExCA Registers and Offsets (continued)EXCA REGISTER NAMEPCI MEMORY ADDRESSOFFSET (HEX)EXCA OFFSET(CARD A)EXCA OFFSET(CARD B)Reserved 826

5−55.1 ExCA Identification and Revision RegisterThis register provides host software with information on 16-bit PC Card support and 82365SL-DF compati

5−65.2 ExCA Interface Status RegisterThis register provides information on current status of the PC Card interface. An X in the default bit values ind

5−75.3 ExCA Power Control RegisterThis register provides PC Card power control. Bit 7 of this register enables the 16-bit outputs on the socket interf

5−85.4 ExCA Interrupt and General Control RegisterThis register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card

5−95.5 ExCA Card Status-Change RegisterThe ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16

5−105.6 ExCA Card Status-Change Interrupt Configuration RegisterThis register controls interrupt routing for CSC interrupts, as well as masks/unmasks

5−115.7 ExCA Address Window Enable RegisterThe ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card.

xivTable Title Page3−18 Function 4 Power-Management Registers 3−26. . . . . . . . . . . . . . . . . . . . . . . . . . 3−19 Function 5 Power-Management

5−125.8 ExCA I/O Window Control RegisterThe ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. SeeTab

5−135.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte RegistersThese registers contain the low byte of the 16-bit I/O window start address for I/O w

5−145.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte RegistersThese registers contain the low byte of the 16-bit I/O window end address for I/O wind

5−155.13 ExCA Memory Windows 0−4 Start-Address Low-Byte RegistersThese registers contain the low byte of the 16-bit memory window start address for me

5−165.14 ExCA Memory Windows 0−4 Start-Address High-Byte RegistersThese registers contain the high nibble of the 16-bit memory window start address fo

5−175.15 ExCA Memory Windows 0−4 End-Address Low-Byte RegistersThese registers contain the low byte of the 16-bit memory window end address for memory

5−185.16 ExCA Memory Windows 0−4 End-Address High-Byte RegistersThese registers contain the high nibble of the 16-bit memory window end address for me

5−195.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte RegistersThese registers contain the low byte of the 16-bit memory window offset address for

5−205.18 ExCA Memory Windows 0−4 Offset-Address High-Byte RegistersThese registers contain the high 6 bits of the 16-bit memory window offset address

5−215.19 ExCA Card Detect and General Control RegisterThis register controls how the ExCA registers for the socket respond to card removal. It also re

xvTable Title Page5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description 5−20. . . . . . . . . . . . . . . . . . . . . . . . . .

5−225.20 ExCA Global Control RegisterThis register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits

5−235.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte RegistersThese registers contain the low byte of the 16-bit I/O window offset address for I/

5−245.23 ExCA Memory Windows 0−4 Page RegistersThe upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when deco

6−16 CardBus Socket Registers (Functions 0 and 1)The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that

6−26.1 Socket Event RegisterThis register indicates a change in socket status has occurred. These bits do not indicate what the change is, onlythat on

6−36.2 Socket Mask RegisterThis register allows software to control the CardBus card events which generate a status change interrupt. The stateof thes

6−46.3 Socket Present State RegisterThis register reports information about the socket interface. Writes to the socket force event register (offset 0C

6−5Table 6−4. Socket Present State Register Description (Continued)BIT SIGNAL TYPE FUNCTION9 † BADVCCREQ RBad VCC request. This bit indicates that th

6−6Table 6−5. Socket Force Event Register DescriptionBIT SIGNAL TYPE FUNCTION31−15 RSVD R Reserved. These bits return 0s when read.14 CVSTEST WCard VS

6−76.5 Socket Control RegisterThis register provides control of the voltages applied to the socket VPP and VCC. The PCI7x21/PCI7x11 controllerensures

xviTable Title Page8−11 Host Controller Control Register Description 8−13. . . . . . . . . . . . . . . . . . . . . . . . 8−12 Self-ID Count Register D

6−86.6 Socket Power Management RegisterThis register provides power management control over the socket through a mechanism for slowing or stopping the

7−17 OHCI Controller Programming ModelThis section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 1394 open ho

7−27.1 Vendor ID RegisterThe vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.The vendor

7−37.3 Command RegisterThe command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhereto the definit

7−47.4 Status RegisterThe status register provides status over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to thedefinition

7−57.5 Class Code and Revision ID RegisterThe class code and revision ID register categorizes the PCI7x21/PCI7x11 controller as a serial bus controlle

7−67.7 Header Type and BIST RegisterThe header type and built-in self-test (BIST) register indicates the PCI7x21/PCI7x11 PCI header type and no built-

7−77.9 TI Extension Base Address RegisterThe TI extension base address register is programmed with a base address referencing the memory-mapped TIexte

7−87.10 CardBus CIS Base Address RegisterThe internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read. S

7−97.12 Subsystem Identification RegisterThe subsystem identification register is used for system and option card identification purposes. This regist

xviiTable Title Page11−5 Latency Timer and Class Cache Line Size Register Description 11−5. . . . . . . 11−6 Header Type and BIST Register Description

7−107.14 Interrupt Line RegisterThe interrupt line register communicates interrupt line routing information. See Table 7−11 for a complete description

7−117.16 Minimum Grant and Maximum Latency RegisterThe minimum grant and maximum latency register communicates to the system the desired setting of bi

7−127.18 Capability ID and Next Item Pointer RegistersThe capability ID and next item pointer register identifies the linked-list capability item and

7−137.19 Power Management Capabilities RegisterThe power management capabilities register indicates the capabilities of the PCI7x21/PCI7x11 controller

7−147.20 Power Management Control and Status RegisterThe power management control and status register implements the control and status of the PCI pow

7−157.22 PCI PHY Control RegisterThe PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7−19 for a completedescript

7−167.23 PCI Miscellaneous Configuration RegisterThe PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Ta

7−17Table 7−20. PCI Miscellaneous Configuration Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION1 ‡DISABLE_PCIGATERWWhen bit 1 is set t

7−18Table 7−21. Link Enhancement Control Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION11 RSVD R Reserved. Bit 11 returns 0 when read

7−197.26 GPIO Control RegisterThe GPIO control register has the control and status bits for GPIO0, GPIO1, GPIO2, and GPIO3 ports. Upon reset,GPIO0 and

xviiiTable Title Page13−15 Smart Card Configuration 1 Register Description 13−16. . . . . . . . . . . . . . . . . . . 13−16 Smart Card Configuration 2

7−20Table 7−23. GPIO Control Register Description (Continued)BIT SIGNAL TYPE FUNCTION12 GPIO_ENB1 R/WGPIO1 enable control. When bit 15 (DISABLE_LPS)

8−18 OHCI RegistersThe OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a2K-byte region of memor

8−2Table 8−1. OHCI Register Map (Continued)DMA CONTEXT REGISTER NAME ABBREVIATION OFFSETSelf-ID Reserved — 60hSelf-ID buffer pointer SelfIDBuffer 64hS

8−3Table 8−1. OHCI Register Map (Continued)DMA CONTEXT REGISTER NAME ABBREVIATION OFFSETAsynchronous context controlContextControlSet 180hAsynchronous

8−48.1 OHCI Version RegisterThe OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. SeeTable 8−2

8−58.2 GUID ROM RegisterThe GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCIversion register at O

8−68.3 Asynchronous Transmit Retries RegisterThe asynchronous transmit retries register indicates the number of times the PCI7x21/PCI7x11 controller a

8−78.5 CSR Compare RegisterThe CSR compare register accesses the bus management CSR registers from the host through compare-swapoperations. This regis

8−88.7 Configuration ROM Header RegisterThe configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offs

8−98.9 Bus Options RegisterThe bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8−7 for a completedescripti

1−11 IntroductionThe Texas Instruments PCI7621 controller is an integrated dual-socket UltraMedia PC Card controller, Smart Cardcontroller, IEEE 1394

8−108.10 GUID High RegisterThe GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the thirdquadlet in t

8−118.12 Configuration ROM Mapping RegisterThe configuration ROM mapping register contains the start address within system memory that maps to the sta

8−128.14 Posted Write Address High RegisterThe posted write address high register communicates error information if a write request is posted and an e

8−138.16 Host Controller Control RegisterThe host controller control set/clear register pair provides flags for controlling the PCI7x21/PCI7x11 contro

8−14Table 8−11. Host Controller Control Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION22 aPhyEnhanceEnable RSC When bits 23 (programP

8−158.18 Self-ID Count RegisterThe self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-IDpack

8−168.19 Isochronous Receive Channel Mask High RegisterThe isochronous receive channel mask high set/clear register enables packet receives from the u

8−17Table 8−13. Isochronous Receive Channel Mask High Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION6 isoChannel38 RSC When bit 6 is

8−188.21 Interrupt Event RegisterThe interrupt event set/clear register reflects the state of the various PCI7x21/PCI7x11 interrupt sources. Theinterr

8−19Table 8−15. Interrupt Event Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION22 cycleLost RSCU A lost cycle is indicated when no cyc

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvemen

1−2Function 5 of the PCI7621 controller is a PCI-based Smart Card controller used for communication with Smart Cardsinserted in PC Card adapters. Util

8−208.22 Interrupt Mask RegisterThe interrupt mask set/clear register enables the various PCI7x21/PCI7x11 interrupt sources. Reads from either theset

8−21Table 8−16. Interrupt Mask Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION18 regAccessFail RSC When this bit and bit 18 (regAccess

8−228.23 Isochronous Transmit Interrupt Event RegisterThe isochronous transmit interrupt event set/clear register reflects the interrupt state of the

8−238.24 Isochronous Transmit Interrupt Mask RegisterThe isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source o

8−248.25 Isochronous Receive Interrupt Event RegisterThe isochronous receive interrupt event set/clear register reflects the interrupt state of the is

8−258.26 Isochronous Receive Interrupt Mask RegisterThe isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on

8−268.28 Initial Channels Available High RegisterThe initial channels available high register value is loaded into the corresponding bus management CS

8−278.30 Fairness Control RegisterThe fairness control register provides a mechanism by which software can direct the host controller to transmitmulti

8−288.31 Link Control RegisterThe link control set/clear register provides the control flags that enable and configure the link core protocol portions

8−298.32 Node Identification RegisterThe node identification register contains the address of the node on which the OHCI-Lynx chip resides, andindica

1−3through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes DMAcapabilities for improved Flash

8−308.33 PHY Layer Control RegisterThe PHY layer control register reads from or writes to a PHY register. See Table 8−25 for a complete description of

8−318.34 Isochronous Cycle Timer RegisterThe isochronous cycle timer register indicates the current cycle number and offset. When the PCI7x21/PCI7x11c

8−328.35 Asynchronous Request Filter High RegisterThe asynchronous request filter high set/clear register enables asynchronous receive requests on a p

8−33Table 8−27. Asynchronous Request Filter High Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION18 asynReqResource50 RSC If bit 18 is

8−348.36 Asynchronous Request Filter Low RegisterThe asynchronous request filter low set/clear register enables asynchronous receive requests on a per

8−358.37 Physical Request Filter High RegisterThe physical request filter high set/clear register enables physical receive requests on a per-node basi

8−36Table 8−29. Physical Request Filter High Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION18 physReqResource50 RSC If bit 18 is set

8−378.38 Physical Request Filter Low RegisterThe physical request filter low set/clear register enables physical receive requests on a per-node basis,

8−388.40 Asynchronous Context Control RegisterThe asynchronous context control set/clear register controls the state and indicates status of the DMA c

8−398.41 Asynchronous Context Command Pointer RegisterThe asynchronous context command pointer register contains a pointer to the address of the first

1−41.2 FeaturesThe PCI7x21/PCI7x11 controller supports the following features:• PC Card Standard 8.1 compliant• PCI Bus Power Management Interface Spe

8−408.42 Isochronous Transmit Context Control RegisterThe isochronous transmit context control set/clear register controls options, state, and status

8−418.43 Isochronous Transmit Context Command Pointer RegisterThe isochronous transmit context command pointer register contains a pointer to the addr

8−42Table 8−34. Isochronous Receive Context Control Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION29 cycleMatchEnable RSCU When bit 2

8−438.45 Isochronous Receive Context Command Pointer RegisterThe isochronous receive context command pointer register contains a pointer to the addres

8−448.46 Isochronous Receive Context Match RegisterThe isochronous receive context match register starts an isochronous receive context running on a s

9−19 TI Extension RegistersThe TI extension base address register provides a method of accessing memory-mapped TI extension registers. SeeSection 7.9,

9−29.2 Isochronous Receive Digital Video EnhancementsThe DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize

9−3Table 9−2. Isochronous Receive Digital Video Enhancements Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION7−6 RSVD R Reserved. Bits

9−49.4 Link Enhancement RegisterThis register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCIof

9−5Table 9−3. Link Enhancement Register Description (Continued)BIT FIELD NAME TYPE DESCRIPTION9 RSVD R Reserved. Bit 9 returns 0 when read.8 ‡ enab_dv

1−5• External cycle timer control for customized synchronization• Extended resume signaling for compatibility with legacy DV components• PHY-Link logi

9−6

10−110 PHY Register ConfigurationThere are 16 accessible internal registers in the PCI7x21/PCI7x11 controller. The configuration of the registers atad

10−2Table 10−2. Base Register Field DescriptionsFIELD SIZE TYPE DESCRIPTIONPhysical ID 6 R This field contains the physical address ID of this node de

10−3Table 10−2. Base Register Field Descriptions (Continued)FIELD SIZE TYPE DESCRIPTIONISBR 1 R/W Initiate short arbitrated bus reset. This bit, if se

10−410.2 Port Status RegisterThe port status page provides access to configuration and status information for each of the ports. The port is selectedb

10−5Table 10−4. Page 0 (Port Status) Register Field Descriptions (Continued)FIELD SIZE TYPE DESCRIPTIONInt_enable 1 RW Port event interrupt enable. Wh

10−610.4 Vendor-Dependent RegisterThe vendor-dependent page provides access to the special control features of the PCI7x21/PCI7x11 controller, aswell

10−710.5 Power-Class ProgrammingThe PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field(bits 21–23

10−8

11−111 Flash Media Controller Programming ModelThis section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 fla

1−6• SD Memory Card Specifications, SD Group, March 2000• Memory Stick Format Specification, Version 2.0 (Memory Stick-Pro)• ISO Standards for Identif

11−211.1 Vendor ID RegisterThe vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.The vend

11−311.3 Command RegisterThe command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhereto the defin

11−411.4 Status RegisterThe status register provides device information to the host system. All bit functions adhere to the definitions in thePCI Loca

11−511.5 Class Code and Revision ID RegisterThe class code and revision ID register categorizes the base class, subclass, and programming interface of

11−611.7 Header Type and BIST RegisterThe header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and

11−711.9 Subsystem Vendor Identification RegisterThe subsystem identification register, used for system and option card identification purposes, may b

11−811.12 Interrupt Line RegisterThe interrupt line register is programmed by the system and indicates to the software which interrupt line the flashm

11−911.14 Minimum Grant RegisterThe minimum grant register contains the minimum grant value for the flash media controller core.Bit 7 6 5 4 3 2 1 0Nam

11−1011.16 Capability ID and Next Item Pointer RegistersThe capability ID and next item pointer register identifies the linked-list capability item an

11−1111.17 Power Management Capabilities RegisterThe power management capabilities register indicates the capabilities of the flash media controller r

1−71.5 Terms and DefinitionsTerms and definitions used in this document are given in Table 1−1.Table 1−1. Terms and DefinitionsTERM DEFINITIONSAT AT (

11−1211.18 Power Management Control and Status RegisterThe power management control and status register implements the control and status of the flash

11−1311.20 Power Management Data RegisterThe power management bridge support extension register provides extended power-management features notapplica

11−1411.22 Subsystem Access RegisterThe contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registersat

11−1511.23 Diagnostic RegisterThis register programs the M and N inputs to the PLL and enables the diagnostic modes. The default values for Mand N in

11−16

12−112 SD Host Controller Programming ModelThis section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 SD host

12−212.1 Vendor ID RegisterThe vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.The vend

12−312.3 Command RegisterThe command register provides control over the SD host controller interface to the PCI bus. All bit functions adhereto the de

12−412.4 Status RegisterThe status register provides device information to the host system. All bit functions adhere to the definitions in thePCI Loca

12−512.5 Class Code and Revision ID RegisterThe class code and revision ID register categorizes the base class, subclass, and programming interface of

1−8

12−612.6 Latency Timer and Class Cache Line Size RegisterThe latency timer and class cache line size register is programmed by host BIOS to indicate s

12−712.8 SD Host Base Address RegisterThe SD host base address register specifies the base address of the memory-mapped interface registers for eachst

12−812.10 Subsystem Identification RegisterThe subsystem identification register, used for system and option card identification purposes, may be requ

12−912.13 Interrupt Pin RegisterThis register decodes the interrupt select inputs and returns the proper interrupt value based on Table 12−8,indicatin

12−1012.15 Maximum Latency RegisterThe maximum latency register contains the maximum latency value for the SD host controller core.Bit 7 6 5 4 3 2 1 0

12−1112.17 Capability ID and Next Item Pointer RegistersThe capability ID and next item pointer register identifies the linked-list capability item an

12−1212.18 Power Management Capabilities RegisterThe power management capabilities register indicates the capabilities of the SD host controller relat

12−1312.19 Power Management Control and Status RegisterThe power management control and status register implements the control and status of the SD ho

12−1412.21 Power Management Data RegisterThe power management bridge support extension register provides extended power-management features notapplica

12−1512.23 Subsystem Access RegisterThe contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registersat

2−12 Terminal DescriptionsThe PCI7x21/PCI7x11 controller is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminallead-free (P

12−1612.25 Slot 0 3.3-V Maximum Current RegisterThis register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CU

12−1712.28 Slot 3 3.3-V Maximum Current RegisterThis register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CU

12−18

13−113 Smart Card Controller Programming ModelThis section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 Smar

13−213.1 Vendor ID RegisterThe vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.The vend

13−313.3 Command RegisterThe command register provides control over the Smart Card controller interface to the PCI bus. All bit functionsadhere to the

13−413.4 Status RegisterThe status register provides device information to the host system. All bit functions adhere to the definitions in thePCI Loca

13−513.5 Class Code and Revision ID RegisterThe class code and revision ID register categorizes the base class, subclass, and programming interface of

13−613.7 Header Type and BIST RegisterThe header type and built-in self-test (BIST) register indicates the Smart Card controller PCI header type and n

13−713.9 Smart Card Base Address Register 1−4Each socket has its own base address register. For example, a device supports three Smart Card sockets us

2−2B_CCLKRUN//B_WP(IOIS16)WPDARTUVMNKLHJFGEBC19151051 14131211 169876432 17 18A_CINT//A_READY(IREQ)A_CAD25//A_A1VCCAA_CAD21//A_A5A_CAD19//A_A25A_CC/BE

13−813.11 Subsystem Identification RegisterThis register is read-update and can be modified through the subsystem ID alias register. This register has

13−913.14 Interrupt Pin RegisterThis register decodes the interrupt select inputs and returns the proper interrupt value based on Table 13−7,indicatin

13−1013.16 Maximum Latency RegisterThe maximum latency register contains the maximum latency value for the Smart Card controller core.Bit 7 6 5 4 3 2

13−1113.18 Power Management Capabilities RegisterThe power management capabilities register indicates the capabilities of the Smart Card controller re

13−1213.19 Power Management Control and Status RegisterThe power management control and status register implements the control and status of the Smart

13−1313.21 Power Management Data RegisterThe power management bridge support extension register provides extended power-management features notapplica

13−1413.23 Subsystem ID Alias RegisterThe contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registersa

13−1513.25 Smart Card Configuration 1 RegisterBIOS or EEPROM configure system dependent Smart Card interface information through this register. Inform

13−16Table 13−15. Smart Card Configuration 1 Register DescriptionBIT FIELD NAME TYPE DESCRIPTION31−28 SCRTCH_PAD RW Scratch pad27 CLASS_B_SKT3 R Socke

13−1713.26 Smart Card Configuration 2 RegisterBIOS or EEPROM configure system dependent Smart Card interface information through this register. Inform

2−3WPDARTUVMNKLHJFGEBC19151051 14131211 169876432 17 18A_CINT//A_READY(IREQ)A_CAD25//A_A1VCCAA_CAD21//A_A5A_CAD19//A_A25A_CC/BE2//A_A12A_CDEVSEL//A_A2

13−18

14−114 Electrical Characteristics14.1 Absolute Maximum Ratings Over Operating Temperature Ranges†Supply voltage range, VR_PORT −0.2 V to 2.2 V. . . .

14−2Recommended Operating Conditions (continued)OPERATION MIN NOM MAX UNITPCIk3.3 V 0.5 VCCPVCCPPCIk5 V 2 VCCP3.3 V CardBus 0.475 VCC(A/B)VCC(A/B)VIH†

14−3Recommended Operating Conditions (continued)OPERATION MIN NOM MAX UNITS100 operation ±1.08Receive input jitter TPA, TPB cable inputsS200 operation

14−414.3 Electrical Characteristics Over Recommended Operating Conditions (unlessotherwise noted)PARAMETER TERMINALS OPERATION TEST CONDITIONS MIN MAX

14−514.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions(unless otherwise noted)14.4.1 DevicePARAMETER TEST CONDITION MIN M

14−614.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of SupplyVoltage and Operating Free-Air TemperaturePARAMETERALTERNATESYMBOLTEST C

15−115 Mechanical InformationThe PCI7x21/PCI7x11 device is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminallead (Pb atom

15−2

PACKAGING INFORMATIONOrderable Device Status(1)PackageTypePackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)PCI7411GHK ACTIVE B

iiiContentsSection Title Page1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4WPDARTUVMNKLHJFGEBC19151051 14131211 169876432 17 18A_CINT//A_READY(IREQ)A_CAD25//A_A1VCCAA_CAD21//A_A5A_CAD19//A_A25A_CC/BE2//A_A12A_CDEVSEL//A_A2

2−5Table 2−1. Signal Names by GHK Terminal NumberTERMINALNUMBERSIGNAL NAMETERMINALNUMBERSIGNAL NAMETERMINALNUMBERCardBus PC Card 16-Bit PC CardTERMINA

2−6Table 2−1. Signal Names by GHK Terminal Number (Continued)TERMINALSIGNAL NAMETERMINALSIGNAL NAMETERMINALNUMBERCardBus PC Card 16-Bit PC CardTERMINA

2−7Table 2−1. Signal Names by GHK Terminal Number (Continued)TERMINALSIGNAL NAMETERMINALSIGNAL NAMETERMINALNUMBERCardBus PC Card 16-Bit PC CardTERMINA

2−8Table 2−1. Signal Names by GHK Terminal Number (Continued)TERMINALSIGNAL NAMETERMINALSIGNAL NAMETERMINALNUMBERCardBus PC Card 16-Bit PC CardTERMINA

2−9Table 2−2. CardBus PC Card Signal Names Sorted AlphabeticallySIGNAL NAMETERMINALNUMBERSIGNAL NAMETERMINALNUMBERSIGNAL NAMETERMINALNUMBERSIGNAL NAME

2−10Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically (Continued)SIGNAL NAMETERMINALNUMBERSIGNAL NAMETERMINALNUMBERSIGNAL NAMETERMINALNUMB

2−11Table 2−3. 16-Bit PC Card Signal Names Sorted AlphabeticallySIGNALNAMETERMINALNUMBERSIGNAL NAMETERMINALNUMBERSIGNAL NAMETERMINALNUMBERSIGNAL NAMET

2−12Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)SIGNAL NAMETERMINALNUMBERSIGNAL NAMETERMINALNUMBERSIGNAL NAMETERMINALNUMBE

2−132.1 Detailed Terminal DescriptionsPlease see Table 2−4 through Table 2−19 for more detailed terminal descriptions. The following list defines thec

ivSection Title Page3.5.8 SPKROUT and CAUDPWM Usage 3−9. . . . . . . . . . . . . . . . . . . 3.5.9 LED Socket Activity Indicators 3−9. . . . . . . . .

2−14Table 2−4. Power Supply TerminalsOutput description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the

2−15Table 2−5. PC Card Power Switch TerminalsInternal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the

2−16Table 2−7. PCI Address and Data TerminalsInternal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data term

2−17Table 2−8. PCI Interface Control TerminalsInternal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control te

2−18Table 2−9. Multifunction and Miscellaneous TerminalsThe power rail designation is not applicable for the multifunction and miscellaneous terminals

2−19Table 2−10. 16-Bit PC Card Address and Data TerminalsExternal components are not applicable for the 16-bit PC Card address and data terminals. If

2−20Table 2−11. 16-Bit PC Card Interface Control TerminalsExternal components are not applicable for the 16-bit PC Card interface control terminals. I

2−21Table 2−11. 16-Bit PC Card Interface Control Terminals (Continued)SKT A TERMINAL SKT B TERMINAL†DESCRIPTIONI/OPOWERNAME NO. NAME NO.DESCRIPTIONI/O

2−22Table 2−12. CardBus PC Card Interface System TerminalsA 33-Ω to 47-Ω series damping resistor (per PC Card specification) is the only external comp

2−23Table 2−13. CardBus PC Card Address and Data TerminalsExternal components are not applicable for the 16-bit PC Card address and data terminals. If

vSection Title Page4 PC Card Controller Programming Model 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 PCI Configuration Register Ma

2−24Table 2−14. CardBus PC Card Interface Control TerminalsIf any CardBus PC Card interface control terminal is unused, then the terminal may be left

2−25Table 2−14. CardBus PC Card Interface Control Terminals (Continued)SKT A TERMINAL SKT B TERMINAL†DESCRIPTIONI/OINPUTOUTPUTPU/POWERNAME NO. NAME NO

2−26Table 2−15. IEEE 1394 Physical Layer TerminalsTERMINALDESCRIPTIONI/OINPUTOUTPUTEXTERNALPIN STRAPPINGNAME NO.DESCRIPTIONI/OTYPEINPUT OUTPUTEXTERNAL

2−27Table 2−16. SD/MMC TerminalsIf any SD/MMC terminal is unused, then the terminal may be left floating.TERMINALDESCRIPTIONI/OINPUTOUTPUTPU/POWEREXTE

2−28Table 2−18. Smart Media/XD TerminalsIf any Smart Media/XD terminal is unused, then the terminal may be left floating.TERMINALDESCRIPTIONI/OINPUTOU

2−29Table 2−19. Smart Card Terminals †If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must be

2−30

3−13 Feature/Protocol DescriptionsThe following sections give an overview of the PCI7x21/PCI7x11 controller. Figure 3−1 shows the connections to thePC

3−23.2 I/O CharacteristicsThe PCI7x21/PCI7x11 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI LocalBus Specif

3−33.4.2 Device ResetsThe following are the requirements for proper reset of the PCI7x21/PCI7x11 controller:1. GRST and PRST must both be asserted at

viSection Title Page4.42 Next Item Pointer Register 4−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.43 Power Management

3−4as bus master, by reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial buscontrol/status register (PCI offset B3

3−53.4.5 Function 2 (OHCI 1394) Subsystem IdentificationThe subsystem identification register is used for system and option card identification purpos

3−63.5.1 PC Card Insertion/Removal and RecognitionThe PC Card Standard (release 8.1) addresses the card-detection and recognition process through an i

3−7Table 3−2. PC Card—Card Detect and Voltage Sense ConnectionsCD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface VCCVPP/VCOREGround Ground Open Op

3−83.5.5 Power Switch InterfaceThe power switch interface of the PCI7x21/PCI7x11 controller is a 3-pin serial interface. This 3-pin interface isimplem

3−93.5.7 Integrated Pullup Resistors for PC Card InterfaceThe PC Card Standard requires pullup resistors on various terminals to support both CardBus

3−10PCI7x21/PCI7x11Current LimitingR ≈ 150 ΩSocket ALEDMFUNCxCurrent LimitingR ≈ 150 ΩSocket BLEDMFUNCyFigure 3−6. Two Sample LED CircuitsAs indicat

3−11• Frequency stability (overtemperature and age): A crystal with ±30 ppm frequency stability is recommendedfor adequate margin.NOTE: The total fre

3−12SDASCLStartConditionStopConditionChange ofData AllowedData Line Stable,Data ValidFigure 3−7. Serial-Bus Start/Stop Conditions and Bit TransfersDat

3−13Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W commandbit must be set to 1 to indica

viiSection Title Page7 OHCI Controller Programming Model 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Vendor ID Register 7−2.

3−14Table 3−9. EEPROM Loading MapSERIAL ROMOFFSETBYTE DESCRIPTION00h CardBus function indicator (00h)01h Number of bytes (20h)PCI 04h, command registe

3−15Table 3−9. EEPROM Loading Map (Continued)SERIAL ROMOFFSETBYTE DESCRIPTION25h PCI 2Ch, subsystem vendor ID, byte 026h PCI 2Dh, subsystem vendor ID,

3−16Table 3−9. EEPROM Loading Map (Continued)SERIAL ROMOFFSETBYTE DESCRIPTION49h PCI 94h, slot 0 3.3 V maximum current4Ah PCI 98h, slot 1 3.3 V maximu

3−173.7.1 PC Card Functional and Card Status Change InterruptsPC Card functional interrupts are defined as requests from a PC Card application for int

3−18Table 3−11. PC Card Interrupt Events and DescriptionCARD TYPE EVENT TYPE SIGNAL DESCRIPTIONBattery conditionsCSCBVD1(STSCHG)//CSTSCHGA transition

3−19Table 3−10 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PCCard-related interrupt fla

3−20The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCIoffset 3Dh, see Section 4.24).

3−21• Ring indicate• PCI power management• Cardbus bridge power management• ACPI supportPCI BusPCI7x21/PCI7x111394aSocketEEPROMPower SwitchSD/MMCPCCar

3−223.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR)The PCI7x21/PCI7x11 controller requires 1.5-V core voltage. The core power can be supplied

3−233.8.5 16-Bit PC Card Power ManagementThe COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN

viiiSection Title Page8.15 Vendor ID Register 8−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 Host Contro

3−24places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to thecontroller unless a PCI transaction

3−253.8.9 PCI Power Management3.8.9.1 CardBus Power Management (Functions 0 and 1)The PCI Bus Power Management Interface Specification for PCI to Card

3−26For more information on PCI power management, see the PCI Bus Power Management Interface Specification forPCI to CardBus Bridges.3.8.9.2 OHCI 1394

3−27The Texas Instruments PCI7x21/PCI7x11 controller addresses these D3 wake-up issues in the following manner:• Two resets are provided to handle pre

3−28• ExCA card status-change interrupt configuration register (ExCA 805h/845h, see Section 5.6): bits 3−0• ExCA card detect and general control regis

3−29The global reset-only (function 3) register bits:• Subsystem vendor ID register (PCI offset 2Ch, see Section 11.9): bits 15–0• Subsystem ID regist

3−303.9 IEEE 1394 Application Information3.9.1 PHY Port Cable ConnectionTPA+TPA−TPB+TPB−Cable PortCPSTPBIAS56 Ω56 Ω56 Ω56 Ω5 kΩ1 µF400 kΩ220 pF(see No

3−31Outer Cable ShieldChassis GroundFigure 3−19. Non-DC Isolated Outer Shield Termination3.9.2 Crystal SelectionThe PCI7x21/PCI7x11 controller is desi

3−32X124.576 MHzISX1CPHY + CBDX0C10C9Figure 3−20. Load Capacitance for the PCI7x21/PCI7x11 PHYThe layout of the crystal portion of the PHY circuit is

3−33Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of theIBR bit, RHB, and Gap_Count i

ixSection Title Page10.4 Vendor-Dependent Register 10−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Power-Class Programmin

3−34

4−14 PC Card Controller Programming ModelThis chapter describes the PCI7x21/PCI7x11 PCI configuration registers that make up the 256-byte PCI configur

4−2Table 4−2. Functions 0 and 1 PCI Configuration Register Map (Continued)REGISTER NAME OFFSETCardBus I/O base register 0 2ChCardBus I/O limit registe

4−34.3 Device ID Register Functions 0 and 1This read-only register contains the device ID assigned by TI to the PCI7x21/PCI7x11 CardBus controller fun

4−44.4 Command RegisterThe PCI command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functionsadhere to the def

4−5Table 4−3. Command Register Description (continued)BITSIGNAL TYPE FUNCTION1 MEM_EN RWMemory space enable. This bit controls whether or not the PCI7

4−6Table 4−4. Status Register Description (continued)BIT SIGNAL TYPE FUNCTION4 CAPLIST RCapabilities list. This bit returns 1 when read. This bit indi

4−74.9 Latency Timer RegisterThe latency timer register specifies the latency timer for the PCI7x21/PCI7x11 controller, in units of PCI clock cycles.W

4−84.12 CardBus Socket Registers/ExCA Base Address RegisterThis register is programmed with a base address referencing the CardBus socket registers an

4−94.14 Secondary Status RegisterThe secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicatesCardBus-re