Texas Instruments PCI445X User Manual

      August 2000 PCI Bus SolutionsImplementationGuideSCPU007

ContentsxTables1–1 Registers and Bits Loadable Through Serial EEPROM 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 PC Card Interface

1-1 PCI445X DeviceThis implementation guide assists platform hardware developers designingwith the PCI445X dual socket PC card and 1394 open host cont

1-2Figure 1–1 illustrates a platform using the PCI445X device along with theTSB41LV03 3-port PHY, which provides the necessary interface to implementa

System Features Selection1-3PCI445X Device1.1 System Features SelectionThis section explains selectable system features. Feature selection is required

System Features Selection1-4automatically assigned on the dedicated SDA and SCL terminals. A pullupresistor (typically 10 kΩ) must be added on SDA and

System Features Selection1-5PCI445X Device1.1.10 Socket Activity LEDsSocket activity signals can be assigned on MFUNC4 (slot 1), MFUNC3 (slot 2),MFUNC

System Features Selection1-61.1.12.3 Asynchronous CSC Interrupt GenerationThe ASYNC_CSC bit (diagnostic register, PCI offset 93h, bit 0) controls theC

System Features Selection1-7PCI445X DeviceCCLK can be slowed down rather than stopped by CCLKRUN. If CCLKRUNis set, the CLKCTRLEN (CardBus socket 20h

System Implementation1-81.2 System ImplementationThis section describes signal connection for each interface, PCI bus, PC cardinterface, I2C interface

System Implementation1-9PCI445X DeviceIDSEL, there is no alternative. If another AD line is to be used for IDSEL,then the system designer must leave t

IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or servic

System Implementation1-101.2.3 PC Card InterfaceThe PC Card interface has two modes: the 16-bit interface mode and theCardBus 32-bit interface mode.

System Implementation1-11PCI445X DeviceTable 1–1.Registers and Bits Loadable Through Serial EEPROMRegister Offset Register Bits Loaded FromEEPROMThe f

System Implementation1-121.3 Sample PCI445X EEPROM Data FileFollowing is an example EEPROM data file used with the PCI445X device:;PCI4450 default EEP

System Implementation1-13PCI445X Device1D 0xFF ;111111111E 0xFF ;111111111F 0xFF ;1111111120 0x00 ;00000000 Flag Byte (if 0xFF do not load Function 0

System Implementation1-141.3.1 P2C Interface for TPS22X6 Power SwitchThe interface between the PCI445X device and TPS22X6 power switch isserialized to

System Implementation1-15PCI445X DeviceIf the third ZV source is not implemented, ZVPCLK and ZVSTAT are notrequired. To support ZV audio, an audio cod

System Implementation1-16Figure 1–6. Distributed DMA Signal ConnectionPCGNTPCREQPCI445XSouthBridge(ex., PIIX4)1.3.5 Requirement of Pullup/Pulldown Res

System Implementation1-17PCI445X DeviceTable 1–3.PCI Bus Interface Pullup Resistor ListPCI Signal Pull-Up VoltageFRAME VCCPTRDY VCCPIRDY VCCPDEVSEL VC

System Implementation1-18Table 1–5.Required Pullup/Pulldown ResistorsSignal Resistor RecommendedValue (Ω)ConditionLPS Pulldown (Default) 1.0 k Require

System Implementation1-19PCI445X Device1.4 BIOS Considerations1.4.1 InitializationThis section explains which registers require initialization, but do

Notational Conventionsiii PrefaceRead This FirstAbout This ManualThis manual is intended to assist the designer who is attempting to implementa solut

System Implementation1-20against unexpected overwriting. The values are system and vendordependent. PC Card 16-bit I/F legacy mode base address regis

System Implementation1-21PCI445X Device2) Register save/restoreRegister content is not preserved in the sleeping state (it depends on thesystem implem

Important Information1-221.5 Important InformationThis section clarifies important system implementation.1.5.1 G_RST Clamping RailG_RST is clamped to

Global Reset Only Bits/PME Context BitsA-1Global Reset Only Bits, PME Context BitsGlobal Reset Only Bits, PME Context BitsTopic PageA.1 Global Reset O

Global Reset Only Bits/PME Context BitsA-2A.1 Global Reset Only Bits/PME Context BitsTable A–1.Global Reset Only Cleared BitsRegister Name Space Offse

Global Reset Only Bits/PME Context BitsA-3Global Reset Only Bits, PME Context BitsTable A–2.PME Context BitsRegister Name Space Offset BitBridge contr

A-4

B-1PME and RI BehaviorPME and RI BehaviorThis appendix clarifies PME and RI signal behavior. These signals areimportant to support the wake-up event f

B-2B.1 PME and RI BehaviorTable B–1.CardBus CTSCHG and Wake-Up Signals Truth TableRINGEN RIMUX RIENB PME_EN PME_STAT RI_OUT/PME MFUNC70 0 0 0 Latched

PCI445X Buffer TypesC-1PCI445X Buffer TypesPCI445X Buffer TypesTopic PageC.1 PCI445X Buffer Types C-2Appendix C

Contentsiventer from items that the system displays (such as prompts, commandoutput, error messages, etc.).Here is a sample program listing:0011 0005

PCI445X Buffer TypesC-2C.1 PCI445X Buffer TypesTable C–1. PCI445X Terminal Function Assignment and Buffer TypesSignal Name Terminal Type Signal Name T

PCI445X Buffer TypesC-3PCI445X Buffer TypesTable C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued)Signal Name Terminal Type Signa

PCI445X Buffer TypesC-4Table C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued)Signal Name Terminal Type Signal Name Terminal Type

PCI445X Buffer TypesC-5PCI445X Buffer TypesTable C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued)Signal Name Terminal Type Signa

PCI445X Buffer TypesC-6Table C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued)Signal Name Terminal Type Signal Name Terminal Type

PCI445X Buffer TypesC-7PCI445X Buffer TypesTable C–2. Buffer Type AbbreviationsBuffer Type DescriptionI/O Standard input/outputI Standard input onlyO

C-8

Trademarksv This syntax shows that .byte must have at least one value parameter, butyou have the option of supplying additional value parameters, sep

vi

Contentsvii Contents1 PCI445X Device 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ContentsviiiA Global Reset Only Bits, PME Context Bits A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 Global

Contentsix Figures1–1 Typical System Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .