3 Registers
Registers
Table 4 lists the memory-mapped registers for the general-purpose input/output (GPIO). See the
device-specific data manual for the memory address of these registers.
Table 4. General-Purpose Input/Output (GPIO) Registers
Offset Acronym Register Description Section
0h PID Peripheral Identification Register Section 3.1
8h BINTEN GPIO Interrupt Per-Bank Enable Register Section 3.2
GPIO Banks 0 and 1
10h DIR01 GPIO Banks 0 and 1 Direction Register Section 3.3
14h OUT_DATA01 GPIO Banks 0 and 1 Output Data Register Section 3.4
18h SET_DATA01 GPIO Banks 0 and 1 Set Data Register Section 3.5
1Ch CLR_DATA01 GPIO Banks 0 and 1 Clear Data Register Section 3.6
20h IN_DATA01 GPIO Banks 0 and 1 Input Data Register Section 3.7
24h SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register Section 3.8
28h CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register Section 3.9
2Ch SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register Section 3.10
30h CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register Section 3.11
34h INTSTAT01 GPIO Banks 0 and 1 Interrupt Status Register Section 3.12
GPIO Banks 2 and 3
38h DIR23 GPIO Banks 2 and 3 Direction Register Section 3.3
3Ch OUT_DATA23 GPIO Banks 2 and 3 Output Data Register Section 3.4
40h SET_DATA23 GPIO Banks 2 and 3 Set Data Register Section 3.5
44h CLR_DATA23 GPIO Banks 2 and 3 Clear Data Register Section 3.6
48h IN_DATA23 GPIO Banks 2 and 3 Input Data Register Section 3.7
4Ch SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register Section 3.8
50h CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register Section 3.9
54h SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register Section 3.10
58h CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register Section 3.11
5Ch INTSTAT23 GPIO Banks 2 and 3 Interrupt Status Register Section 3.12
GPIO Bank 4
60h DIR4 GPIO Bank 4 Direction Register Section 3.3
64h OUT_DATA4 GPIO Bank 4 Output Data Register Section 3.4
68h SET_DATA4 GPIO Bank 4 Set Data Register Section 3.5
6Ch CLR_DATA4 GPIO Bank 4 Clear Data Register Section 3.6
70h IN_DATA4 GPIO Bank 4 Input Data Register Section 3.7
74h SET_RIS_TRIG4 GPIO Bank 4 Set Rising Edge Interrupt Register Section 3.8
78h CLR_RIS_TRIG4 GPIO Bank 4 Clear Rising Edge Interrupt Register Section 3.9
7Ch SET_FAL_TRIG4 GPIO Bank 4 Set Falling Edge Interrupt Register Section 3.10
80h CLR_FAL_TRIG4 GPIO Bank 4 Clear Falling Edge Interrupt Register Section 3.11
84h INTSTAT4 GPIO Bank 4 Interrupt Status Register Section 3.12
16 General-Purpose Input/Output (GPIO) SPRUE25 – December 2005
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