TMS320C645x DSPEthernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)User's GuideLiterature Number: SPRU975BAugust 2006
PrefaceSPRU975B – August 2006Read This FirstAbout This ManualThis document provides a functional description of the Ethernet Media Access Controller (
www.ti.com5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)EMAC Port RegistersThe MAC interrupt status (unmasked) register (MACINTSTATRAW)
www.ti.com5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)EMAC Port RegistersThe MAC interrupt status (masked) register (MACINTSTATMASKE
www.ti.com5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)EMAC Port RegistersThe MAC interrupt mask set register (MACINTMASKSET) is shown in Figur
www.ti.com5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)EMAC Port RegistersThe MAC interrupt mask clear register (MACINTMASKCLEAR) is shown
www.ti.com5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)EMAC Port RegistersThe receive multicast/broadcast/promisc
www.ti.comEMAC Port RegistersTable 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) FieldDescriptions (continued)Bit
www.ti.com5.22 Receive Unicast Enable Set Register (RXUNICASTSET)EMAC Port RegistersTable 49. Receive Multicast/Broadcast/Promiscuous Channel Enable R
www.ti.com5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)EMAC Port RegistersThe receive unicast clear register (RXUNICASTCLEAR) is shown in Figur
www.ti.com5.24 Receive Maximum Length Register (RXMAXLEN)EMAC Port RegistersThe receive maximum length register (RXMAXLEN) is shown in Figure 52 and d
www.ti.com5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)EMAC Port RegistersThe receive buffer offset register (RXBUFFEROFFSET) is shown in Figur
1 Introduction1.1 Purpose of the Peripheral1.2 FeaturesUser's GuideSPRU975B – August 2006Ethernet Media Access Controller (EMAC)/ManagementData I
www.ti.com5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)EMAC Port RegistersThe receive filter low priority frame thresh
www.ti.com5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH)EMAC Port RegistersThe receive channel 0-7 flow control threshold r
www.ti.com5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)EMAC Port RegistersThe receive channel 0-7 free buffer count register (RX
www.ti.com5.29 MAC Control Register (MACCONTROL)EMAC Port RegistersThe MAC control register (MACCONTROL) is shown in Figure 57 and described in Table
www.ti.comEMAC Port RegistersTable 57. MAC Control Register (MACCONTROL) Field Descriptions (continued)Bit Field Value Description1 Receive flow contr
www.ti.com5.30 MAC Status Register (MACSTATUS)EMAC Port RegistersThe MAC status register (MACSTATUS) is shown in Figure 58 and described in Table 58 .
www.ti.comEMAC Port RegistersTable 58. MAC Status Register (MACSTATUS) Field Descriptions (continued)Bit Field Value Description15-12 RXERRCODE Receiv
www.ti.com5.31 Emulation Control Register (EMCONTROL)EMAC Port RegistersThe emulation control register (EMCONTROL) is shown in Figure 59 and described
www.ti.com5.32 FIFO Control Register (FIFOCONTROL)EMAC Port RegistersThe FIFO control register (FIFOCONTROL) is shown in Figure 60 and described in Ta
www.ti.com5.33 MAC Configuration Register (MACCONFIG)EMAC Port RegistersThe MAC configuration register (MACCONFIG) is shown in Figure 61 and described
www.ti.com1.3 Functional Block DiagramConfiguration busDMA memorytransfer controllerPeripheral busEMAC control moduleEMAC module MDIO moduleMII MDIO b
www.ti.com5.34 Soft Reset Register (SOFTRESET)EMAC Port RegistersThe Soft Reset Register (SOFTRESET) is shown in Figure 62 and described in Table 62 .
www.ti.com5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)EMAC Port RegistersThe MAC source address low bytes register (MACSRCADDRLO) is show
www.ti.com5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)EMAC Port RegistersThe MAC Source Address High Bytes Register (MACSRCADDRHI) is sh
www.ti.com5.37 MAC Hash Address Register 1 (MACHASH1)EMAC Port RegistersThe MAC hash registers allow group addressed frames to be accepted on the basi
www.ti.com5.38 MAC Hash Address Register 2 (MACHASH2)EMAC Port RegistersThe MAC hash address register 2 (MACHASH2) is shown in Figure 66 and described
www.ti.com5.39 Back Off Test Register (BOFFTEST)EMAC Port RegistersThe back off test register (BOFFTEST) is shown in Figure 67 and described in Table
www.ti.com5.40 Transmit Pacing Algorithm Test Register (TPACETEST)EMAC Port RegistersThe Transmit Pacing Algorithm Test Register (TPACETEST) is shown
www.ti.com5.41 Receive Pause Timer Register (RXPAUSE)EMAC Port RegistersThe receive pause timer register (RXPAUSE) is shown in Figure 69 and described
www.ti.com5.42 Transmit Pause Timer Register (TXPAUSE)EMAC Port RegistersThe Transmit Pause Timer Register (TXPAUSE) is shown in Figure 70 and describ
www.ti.com5.43 MAC Address Low Bytes Register (MACADDRLO)EMAC Port RegistersThe MAC address low bytes register (MACADDRLO) is shown in Figure 71 and d
www.ti.com1.4 Industry Standard(s) Compliance StatementIntroductionThe EMAC peripheral conforms to the IEEE 802.3 standard, describing the “Carrier Se
www.ti.com5.44 MAC Address High Bytes Register (MACADDRHI)EMAC Port RegistersThe MAC address high bytes register (MACADDRHI) is shown in Figure 72 and
www.ti.com5.45 MAC Index Register (MACINDEX)EMAC Port RegistersThe MAC index register (MACINDEX) is shown in Figure 73 and described in Table 73 .Figu
www.ti.com5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)EMAC Port RegistersThe transmit channel 0-7 DMA head descriptor point
www.ti.com5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)EMAC Port RegistersThe receive channel 0-7 DMA head descriptor pointer
www.ti.com5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP)EMAC Port RegistersThe Transmit Channel 0-7 Completion Pointer Register (TX nC
www.ti.com5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP)EMAC Port RegistersThe receive channel 0-7 completion pointer register (RX nCP)
www.ti.com5.50 Network Statistics Registers5.50.1 Good Receive Frames Register (RXGOODFRAMES)5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES)E
www.ti.com5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES)5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES)5.50.5 Receive CRC Errors Regist
www.ti.com5.50.7 Receive Oversized Frames Register (RXOVERSIZED)5.50.8 Receive Jabber Frames Register (RXJABBER)5.50.9 Receive Undersized Frames Regis
www.ti.com5.50.11 Filtered Receive Frames Register (RXFILTERED)5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED)5.50.13 Receive Octet Frame
www.ti.com2 EMAC Functional Architecture2.1 Clock Control2.1.1 MII Clocking2.1.2 RMII Clocking2.1.3 GMII ClockingEMAC Functional ArchitectureThis chap
www.ti.com5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES)5.50.17 Pause Transmit F
www.ti.com5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL)5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL)5.50.22 Tra
www.ti.com5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)5.50.26 Transmit Octet Frames Register (TXOCTETS)5.50.27 Transmit and Receive
www.ti.com5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (
www.ti.com5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (R
www.ti.comAppendix A GlossaryAppendix ABroadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet deviceson the local ne
www.ti.comAppendix AJumbo Packets — Jumbo frames are defined as those packets whose length exceeds the standardEthernet MTU, which is 1500 kbytes. For
www.ti.comAppendix B Revision HistoryAppendix BTable B-1 lists the changes made since the previous version of this document.Table B-1. Document Revisi
IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvemen
www.ti.com2.1.4 RGMII Clocking2.2 Memory MapEMAC Functional ArchitectureFor timing purposes, data in 10/100 mode is transmitted and received with refe
www.ti.com2.3 System Level Connections2.3.1 Media Independent Interface (MII) ConnectionsMTCLKMTXD[3−0]MTXENMCOLMCRSMRCLKMRXD[3−0]MRXDVMRXERMDCLKMDIOP
www.ti.comEMAC Functional ArchitectureTable 2 summarizes the individual EMAC and MDIO signals for the MII interface. For more information,refer to eit
www.ti.com2.3.2 Reduced Media Independent Interface (RMII) ConnectionsMTXD[1−0]MTXENMCRSDVMREFCLKMRXD[1−0]MRXERMDCLKMDIOPhysicallayerdevice(PHY)System
www.ti.comEMAC Functional ArchitectureThe RMII interface has the same functionality as the MII, but it does so with a reduced number of pins,thus lowe
2 SPRU975B – August 2006Submit Documentation Feedback
www.ti.com2.3.3 Gigabit Media Independent Interface (GMII) ConnectionsMTCLKMTXD[7−0]MTXENMCOLMCRSMRCLKMRXD[7−0]MRXDVMRXERMDCLKMDIOPhysicallayerdevice(
www.ti.comEMAC Functional ArchitectureTable 4 summarizes the individual EMAC and MDIO signals for the GMII interface.Table 4. EMAC and MDIO Signals fo
www.ti.com2.3.4 Reduced Gigabit Media Independent Interface (RGMII) ConnectionsTXCTXD[3−0]TXCTLREFCLKRXCRXD[3−0]RXCTLMDCLKMDIOPhysicallayerdevice(PHY)
www.ti.comEMAC Functional ArchitectureTable 5 summarizes the individual EMAC and MDIO signals for the RGMII interface.Table 5. EMAC and MDIO Signals f
www.ti.com2.4 Ethernet Protocol Overview2.4.1 Ethernet Frame FormatPreamble SFD Destination Source Len Data7 1 6 6 2 46 − (RXMAXLEN - 18) 4FCSNumber o
www.ti.com2.4.2 Multiple Access ProtocolEMAC Functional ArchitectureNodes in an ethernet local area network are interconnected by a broadcast channel.
www.ti.com2.5 Programming Interface2.5.1 Packet Buffer DescriptorsEMAC Functional ArchitectureThe buffer descriptor is a central part of the EMAC modu
www.ti.comSOP | EOP 600 60pBufferpNextPacket A60 bytes0SOPFragment 1Packet B5121514pBufferpNext512 bytesEOP00−−−Packet BFragment 3500 bytes502pBuffer−
www.ti.com2.5.2 Transmit and Receive Descriptor QueuesEMAC Functional ArchitectureThe EMAC module processes descriptors in linked list chains (Section
www.ti.com2.5.3 Transmit and Receive EMAC InterruptsEMAC Functional ArchitectureThe EMAC processes descriptors in linked list chains (Section 2.5.1 ),
ContentsPreface ... 101 Int
www.ti.com2.5.4 Transmit Buffer Descriptor FormatEMAC Functional ArchitectureA transmit (TX) buffer descriptor (Figure 9 ) is a contiguous block of fo
www.ti.com2.5.4.1 Next Descriptor Pointer2.5.4.2 Buffer Pointer2.5.4.3 Buffer Offset2.5.4.4 Buffer Length2.5.4.5 Packet Length2.5.4.6 Start of Packet
www.ti.com2.5.4.7 End of Packet (EOP) Flag2.5.4.8 Ownership (OWNER) Flag2.5.4.9 End of Queue (EOQ) Flag2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag2.5
www.ti.com2.5.5 Receive Buffer Descriptor FormatEMAC Functional ArchitectureA receive (RX) buffer descriptor (Figure 10 ) is a contiguous block of fou
www.ti.com2.5.5.1 Next Descriptor Pointer2.5.5.2 Buffer Pointer2.5.5.3 Buffer Offset2.5.5.4 Buffer Length2.5.5.5 Packet LengthEMAC Functional Architec
www.ti.com2.5.5.6 Start of Packet (SOP) Flag2.5.5.7 End of Packet (EOP) Flag2.5.5.8 Ownership (OWNER) Flag2.5.5.9 End of Queue (EOQ) Flag2.5.5.10 Tear
www.ti.com2.5.5.14 Fragment Flag2.5.5.15 Undersized Flag2.5.5.16 Control Flag2.5.5.17 Overrun Flag2.5.5.18 Code Error (CODEERROR) Flag2.5.5.19 Alignme
www.ti.com2.6 EMAC Control ModuleArbiter andbus switchesCPUDMA Controllers8K bytedescriptormemoryConfigurationregistersInterruptlogicSingle interruptt
www.ti.com2.6.3 Interrupt Control2.7 Management Data Input/Output (MDIO) Module2.7.1 MDIO Module ComponentsEMAC Functional ArchitectureThe EMAC contro
www.ti.comEMACcontrolmoduleControlregistersand logicPHYmonitoringPeripheralclockMDIOclockgeneratorUSERINTMDIOinterfacepollingPHYMDCLKMDIOLINKINTConfig
4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) ... 805 EMAC Port Registers ...
www.ti.com2.7.2 MDIO Module Operational Overview2.7.2.1 Initializing the MDIO ModuleEMAC Functional ArchitectureThe MDIO module implements the 802.3 s
www.ti.com2.7.2.2 Writing Data to a PHY Register2.7.2.3 Reading Data From a PHY Register2.7.2.4 Example of MDIO Register Access CodeEMAC Functional Ar
www.ti.comEMAC Functional ArchitectureThe implementation of these macros using the register layer Chip Support Library (CSL) is shown inExample 3 (USE
www.ti.com2.8 EMAC Module2.8.1 EMAC Module ComponentsClock andreset logicReceiveDMA engineInterruptcontrollerTransmitDMA engineControlregistersConfigu
www.ti.com2.8.1.3 MAC Receiver2.8.1.4 Receive Address2.8.1.5 Transmit DMA Engine2.8.1.6 Transmit FIFO2.8.1.7 MAC Transmitter2.8.1.8 Statistics Logic2.
www.ti.com2.8.1.12 Clock and Reset Logic2.8.2 EMAC Module Operational OverviewEMAC Functional ArchitectureThe clock and reset sub-module generates all
www.ti.com2.9 Media Independent Interfaces2.9.1 Data Reception2.9.1.1 Receive Control2.9.1.2 Receive Inter-Frame Interval2.9.1.3 Receive Flow ControlE
www.ti.com2.9.1.4 Collision-Based Receive Buffer Flow Control2.9.1.5 IEEE 802.3X Based Receive Buffer Flow ControlEMAC Functional ArchitectureCollisio
www.ti.com2.9.2 Data Transmission2.9.2.1 Transmit Control2.9.2.2 CRC Insertion2.9.2.3 Adaptive Performance Optimization (APO)2.9.2.4 Interpacket-Gap (
www.ti.com2.9.2.6 Transmit Flow Control2.9.2.7 Speed, Duplex, and Pause Frame SupportEMAC Functional ArchitectureWhen enabled, incoming pause frames a
5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) ... 1345.49 Receive Channel 0-7 Completion Poin
www.ti.com2.10 Packet Receive Operation2.10.1 Receive DMA Host Configuration2.10.2 Receive Channel EnablingEMAC Functional ArchitectureTo configure th
www.ti.com2.10.3 Receive Channel Addressing2.10.4 Hardware Receive QOS SupportEMAC Functional ArchitectureThe receive address block can store up to 32
www.ti.com2.10.5 Host Free Buffer Tracking2.10.6 Receive Channel Teardown2.10.7 Receive Frame ClassificationEMAC Functional ArchitectureThe host must
www.ti.com2.10.8 Promiscuous Receive ModeEMAC Functional ArchitectureWhen the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RX
www.ti.com2.10.9 Receive OverrunEMAC Functional ArchitectureTable 8. Receive Frame Treatment Summary (continued)RXMBPENABLE BitsADDRESS MATCH RXCAFEN
www.ti.com2.11 Packet Transmit Operation2.11.1 Transmit DMA Host Configuration2.11.2 Transmit Channel Teardown2.12 Receive and Transmit LatencyEMAC Fu
www.ti.com2.13 Transfer Node Priority2.14 Reset Considerations2.14.1 Software Reset Considerations2.14.2 Hardware Reset ConsiderationsEMAC Functional
www.ti.com2.15 Initialization2.15.1 Enabling the EMAC/MDIO Peripheral2.15.2 EMAC Control Module InitializationEMAC Functional ArchitectureWhen the dev
www.ti.com2.15.3 MDIO Module InitializationEMAC Functional ArchitectureExample 4. EMAC Control Module Initialization CodeUint32 tmpval;/*// Globally d
www.ti.com2.15.4 EMAC Module InitializationEMAC Functional ArchitectureThe EMAC module sends and receives data packets over the network by maintaining
List of Figures1 EMAC and MDIO Block Diagram ... 122 Ethernet Con
www.ti.com2.16 Interrupt Support2.16.1 EMAC Module Interrupt Events and Requests2.16.1.1 Transmit Packet Completion InterruptsEMAC Functional Architec
www.ti.com2.16.1.2 Receive Packet Completion Interrupts2.16.1.3 Statistics InterruptEMAC Functional ArchitectureThe receive DMA engine has eight chann
www.ti.com2.16.1.4 Host Error Interrupt2.16.2 MDIO Module Interrupt Events and Requests2.16.2.1 Link Change Interrupt2.16.2.2 User Access Completion I
www.ti.com2.16.3 Proper Interrupt Processing2.16.4 Interrupt Multiplexing2.17 Power Management2.18 Emulation ConsiderationsEMAC Functional Architectur
www.ti.com3 EMAC Control Module Registers3.1 Introduction3.2 EMAC Control Module Interrupt Control Register (EWCTL)EMAC Control Module RegistersTable
www.ti.com3.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)EMAC Control Module RegistersThe EMAC control module interrupt timer count
www.ti.com4 MDIO Registers4.1 IntroductionMDIO RegistersTable 14 lists the memory-mapped registers for the Management Data Input/Output (MDIO). See th
www.ti.com4.2 MDIO Version Register (VERSION)MDIO RegistersThe MDIO version register (VERSION) is shown in Figure 16 and described in Table 15 .Figure
www.ti.com4.3 MDIO Control Register (CONTROL)MDIO RegistersThe MDIO control register (CONTROL) is shown in Figure 17 and described in Table 16 .Figure
www.ti.com4.4 PHY Acknowledge Status Register (ALIVE)MDIO RegistersThe PHY acknowledge status register (ALIVE) is shown in Figure 18 and described in
53 Receive Buffer Offset Register (RXBUFFEROFFSET) ... 10954 Receive Filter Low Priority Fr
www.ti.com4.5 PHY Link Status Register (LINK)MDIO RegistersThe PHY link status register (LINK) is shown in Figure 19 and described in Table 18 .Figure
www.ti.com4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)MDIO RegistersThe MDIO link status change interrupt (unmasked) registe
www.ti.com4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)MDIO RegistersThe MDIO link status change interrupt (masked) register
www.ti.com4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)MDIO RegistersThe MDIO user command complete interrupt (unmasked) r
www.ti.com4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)MDIO RegistersThe MDIO user command complete interrupt (Masked) re
www.ti.com4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)MDIO RegistersThe MDIO user command complete interrupt mask set
www.ti.com4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)MDIO RegistersThe MDIO user command complete interrupt mask
www.ti.com4.12 MDIO User Access Register 0 (USERACCESS0)MDIO RegistersThe MDIO user access register 0 (USERACCESS0) is shown in Figure 26 and describe
www.ti.com4.13 MDIO User PHY Select Register 0 (USERPHYSEL0)MDIO RegistersThe MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 27 and
www.ti.com4.14 MDIO User Access Register 1 (USERACCESS1)MDIO RegistersThe MDIO user access register 1 (USERACCESS1) is shown in Figure 28 and describe
List of Tables1 Interface Selection Pins ... 162 EMAC
www.ti.com4.15 MDIO User PHY Select Register 1 (USERPHYSEL1)MDIO RegistersThe MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 29 and
www.ti.com5 EMAC Port Registers5.1 IntroductionEMAC Port RegistersTable 29 lists the memory-mapped registers for the Ethernet Media Access Controller
www.ti.comEMAC Port RegistersTable 29. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Register Description Section15Ch RX
www.ti.comEMAC Port RegistersTable 29. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Register Description Section658h TX
www.ti.comEMAC Port RegistersTable 29. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Register Description Section270h FR
www.ti.com5.2 Transmit Identification and Version Register (TXIDVER)EMAC Port RegistersThe transmit identification and version register (TXIDVER) is s
www.ti.com5.3 Transmit Control Register (TXCONTROL)EMAC Port RegistersThe transmit control register (TXCONTROL) is shown in Figure 31 and described in
www.ti.com5.4 Transmit Teardown Register (TXTEARDOWN)EMAC Port RegistersThe transmit teardown register (TXTEARDOWN) is shown in Figure 32 and describe
www.ti.com5.5 Receive Identification and Version Register (RXIDVER)EMAC Port RegistersThe receive identification and version register (RXIDVER) is sho
www.ti.com5.6 Receive Control Register (RXCONTROL)EMAC Port RegistersThe receive control register (RXCONTROL) is shown in Figure 34 and described in T
50 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ... 10651 Receive Unicast Clear Register (RX
www.ti.com5.7 Receive Teardown Register (RXTEARDOWN)EMAC Port RegistersThe receive teardown register (RXTEARDOWN) is shown in Figure 35 and described
www.ti.com5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)EMAC Port RegistersThe transmit interrupt status (unmasked) register (TXINTS
www.ti.com5.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)EMAC Port RegistersThe transmit interrupt status (Masked) register (TXINTST
www.ti.com5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET)EMAC Port RegistersThe transmit interrupt mask set register (TXINTMASKSET) is shown
www.ti.com5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)EMAC Port RegistersThe transmit interrupt mask clear register (TXINTMASKCLEAR) i
www.ti.com5.12 MAC Input Vector Register (MACINVECTOR)EMAC Port RegistersThe MAC input vector register (MACINVECTOR) is shown in Figure 40 and describ
www.ti.com5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)EMAC Port RegistersThe receive interrupt status (Unmasked) register (RXINTST
www.ti.com5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)EMAC Port RegistersThe receive interrupt status (Masked) register (RXINTSTA
www.ti.com5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)EMAC Port RegistersThe receive interrupt mask set register (RXINTMASKSET) is shown in
www.ti.com5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)EMAC Port RegistersThe receive interrupt mask clear register (RXINTMASKCLEAR) is
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