Texas Instruments TCM4300 User Manual

Data Manual1996 Mixed-Signal Products

1–21.2 TCM4300 Functional Block DiagramTXQPTXQNRSSIBATA/DOUT1FMRXENIQRXENTXENSCENSYNOLTXONINDSYNCLKSYNDTASYNLE[2:0]LCDCONTRD/ATXIPTXINFMRXQPRXQNA/DRXI

1–31.3 Pin Assignments12345678910111213141516171819202122232425767778798081828384858687888990919293949596979899100757473727170696867666564636261605958

1–41.4 Terminal FunctionsTERMINALI/ODESCRIPTIONNAME NO.I/ODESCRIPTIONAFC 11 O Automatic frequency control. The AFC DAC output provides the means to ad

1–51.4 Terminal Functions (Continued)TERMINALI/ODESCRIPTIONNAME NO.I/ODESCRIPTIONDSPRW 69 I DSP read/write. A high on DSPRW enables a read operation a

1–61.4 Terminal Functions (Continued)TERMINALI/ODESCRIPTIONNAME NO.I/ODESCRIPTIONMCDS 48 I Microcontroller data strobe. MCDS is configured by the sign

1–71.4 Terminal Functions (Continued)TERMINALI/ODESCRIPTIONNAME NO.I/ODESCRIPTIONSCEN 94 O Speech CODEC enable. A high out from SCEN can enable the sp

2–12 Electrical SpecificationsThis section lists the electrical specifications, the absolute maximum ratings, the recommended operatingconditions and

2–22.3 Recommended Operating ConditionsMIN NOM MAX UNITSupply voltage, DVDD3 5.5 VHigh-level input voltage, VIHDigital 0.7 DVDDDVDD+0.3 VLow-level inp

2–32.4.3 Terminal ImpedanceFUNCTION MIN TYP†MAX UNITReceive channel input impedance (single ended), RXIP/N and RXQP/N 40 70 kΩTransmit channel output

2–42.4.5 Transmit I and Q Channel OutputsPARAMETER MIN TYP MAX UNITPeak output voltage full scale centered at VCMDifferential 2.24VpPeak output voltag

Printed in U.S.A.10/96SLWS010F

2–52.4.7 Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT)AUXFS[1:0]SETTINGSLOPENOMINAL LSBVALUE(V)NOMINAL OUTPUT VOLTAGEFOR DIGITAL CODE = 128(MIDRA

2–62.5 Operating Characteristics Over Full Range of Operating Conditions(Unless Otherwise Noted)2.5.1 Receive (RX) Channel Frequency Response (RXI, RX

2–72.5.4 Transmit (TX) Channel Frequency Response (Analog Mode)PARAMETER TEST CONDITIONS MIN TYP MAX UNITF0 kHz to 8 kHz (see Note 4) ±0.5dBF8 kHz to

2–8

3–13 Parameter Measurement InformationThis section contains the timing waveforms and parameter values for MCLKOUT and severalmicrocontroller interface

3–23.2 TCM4300 to Microcontroller Interface Timing Requirements (MitsubishiRead Cycle) (see Figure 3–2 and Note 2)PARAMETERALTERNATESYMBOLMIN MAXUNITt

3–33.3 TCM4300 to Microcontroller Interface Timing Requirements (MitsubishiWrite Cycle) (see Figure 3–3 and Note 2)PARAMETERALTERNATESYMBOLMIN MAXUNIT

3–43.4 TCM4300 to Microcontroller Interface Timing Requirements (Intel ReadCycle) (see Figure 3–4 and Note 3)PARAMETERALTERNATESYMBOLMIN MAXUNITtsu(RA

3–53.5 TCM4300 to Microcontroller Interface Timing Requirements (Intel WriteCycle) (see Figure 3–5 and Note 3)PARAMETERALTERNATESYMBOLMIN MAXUNITtsu(W

3–63.6 TCM4300 to Microcontroller Interface Timing Requirements (Motorola16-Bit Read Cycle) (see Figure 3–6 and Note 4)PARAMETERALTERNATESYMBOLMIN MAX

TCM4300Data ManualAdvanced RF Cellular Telephone Interface Circuit(ARCTIC )SLWS010FOctober 1996Printed on Recycled Paper

3–73.7 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 16-Bit Write Cycle) (see Figure 3–7 and Note 4)PARAMETERALTERNATESYMBOLMIN M

3–83.8 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-BitRead Cycle) (see Figure 3–8 and Note 5)PARAMETERALTERNATESYMBOLMIN MAXU

3–93.9 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-BitWrite Cycle) (see Figure 3–9 and Note 5)PARAMETERALTERNATESYMBOLMIN MAX

3–103.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) (seeFigure 3–10)PARAMETERALTERNATESYMBOLMIN MAXUNITtsu(R/W)Setup time, read/

3–113.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) (seeFigure 3–11)PARAMETERALTERNATESYMBOLMIN MAXUNITtsu(R/W)Setup time, read

3–12

4–14 Principles of OperationThis section describes the operation of the TCM4300 in detail.NOTE:Timing diagrams and associated tables are contained in

4–2Table 4–2. RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V)PARAMETER TEST CONDITIONS MIN TYP MAX UNITInput voltage range 0.3 AVDD–0.3 VIn

4–3Table 4–3. Receive (RX) Channel Frequency Response (FM Input in Analog Mode)PARAMETER TEST CONDITIONS MIN TYP MAX UNITF25V k k0 kHz to 6 kHz (see N

4–4square-root raised-cosine (SQRC) shaping filter with a roll-off rate of α = 0.35 and converted to sampledanalog form by two 9-bit digital-to-analog

IMPORTANT NOTICETexas Instruments (TI) reserves the right to make changes to its products or to discontinue anysemiconductor product or service withou

4–5Table 4–6. Transmit (TX) Channel Frequency Response (Digital Mode)PARAMETER TEST CONDITIONS MIN TYP MAX UNITF0 kHz to 8 kHz (see Note 4) ±0.3dBF8 k

4–6delay after the last symbol occurs (2 SINT periods before TXGO goes low); then the transmit outputs decayto zero differential voltage (each output

4–7DQCLKDibitInTXGODQCLKSINTBST OffsetDelayChannel Delay(15.5 SINT Periods)TXI,TXQBST OffsetDelayPAEN DelayPAENDelay = 0, 1/4, 1/2, 3/4Transmit Channe

4–8Table 4–8. Typical Bit-Error-Rate Performance (WBD_BW = 000)PARAMETERTEST CONDITIONSMINMAXUNITPARAMETERMEAN CNRMINMAXUNITBi–50.4dBBi00.279dBBi50.14

4–9At the same time, the interrupts DWBDINT and MWBDFINT are asserted. The interrupt rate is 800 µs(8 bits/10 kHz). These interrupts are individually

4–104.9 Auxiliary DACs, LCD Contrast ConverterAuxiliary DACs generate AFC, AGC and power control signals for the RF system. These three D/Aconverters

4–114.9 Auxiliary DACs, LCD Contrast Converter (continued)Table 4–12. Auxiliary D/A Converters Slope (LCDCONTR)AUXFS[1:0]SETTINGSLOPENOMINAL LSBVALUE(

4–12CMCLKCSCLKCodec Master Clock 2.048 MHzCodec Sample Clock 8 kHzFigure 4–4. Codec Master and Sample Clock Timing4.11.1 Clock GenerationThere are thr

4–134.11.5 Phase-Adjustment StrategyFor an IS-54 system in the digital mode, receiver sample timing must be phase adjusted to synchronize theA/D conve

4–14÷ 17, 18, 19, 20AdjustCounter B= 0 ÷ 256Bits 0–5RCOAdjustCounter A÷ 3, 4, 5Phase-Adjusted9.72-MHz Clock÷ 243/÷ 200ClockDividerChainAnalog/DigitalM

iiiContentsSection Title Page1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–154.12 Frequency Synthesizer InterfaceThe synthesizer interface provides a means of programming three synthesizers. The synthesizer-sideoutputs are

4–16DEDEDESEL 0SEL 1SEL 2SRABAA = BA = BBAB ≤ ABClockCircuitHIGHVALDMUXLOWVALNUMCLKS5BIT CNT[0 . . . 31]MUX3232-Bit DataRegister8ControlRegisters5553R

4–17The SynData0 register contains the least significant bits of the 32-bit data register. SynData3 contains themost significant bits. The bits in the

4–18Up to 31 data bits plus a latch enable (SYNLE0,1,2) can be programmed in one programming cycle. Whendata greater than or equal to 32 bits must be

4–19In addition to allowing control of power to external functional modules, these power control bits combinedwith other control bits are used to cont

4–20In the analog mode, (MODE bit set low), PAEN is high whenever TXEN is active and SYNOL is low. TheSYNOL input can be used as an indication to the

4–214.15 Microcontroller Register MapThe microcontroller can access 17 locations within the TCM4300. The register locations are 8 bits wide asshown in

4–22Table 4–17. Microcontroller Register DefinitionsADDR NAME CATEGORY R/W00h WBDCtrlWide-band dataW00h WBDWide-band dataR01h FIFO FIFO A(B) microcont

4–23Table 4–18. WBDCtrl RegisterBIT R/W NAME FUNCTION RESET VALUE9 R/W WBD_LCKDWide-band data lock data. WBD_LCKD determines whether edgedetector is l

4–24Table 4–19. MStatCtrl Register BitsBIT R/W NAME FUNCTION RESET VALUE7 R SYNOLSynthesizer out of lock. SYNOL is equal to the level applied to SYNOL

iv3.9 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-Bit Write Cycle) 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–254.19 DSP Register MapThe register map accessible to the DSP port is shown in Table 4–20 and Table 4–21. There are 14 systemaddressable locations.

4–26D[15:6]A[3:0]ISR/WSTRBINT 1INT 3INT 4DSPD[9:0]DSPA[3:0]DSPCSLDSPRWDSPSTRBLSINTCINTBDINTDSPTCM4300104Figure 4–11. DSP Interface4.20 Wide-Band Data

4–274.22 DSP Status and Control RegistersDIntCtrl, Clear and Send Bits: The bit names in the DIntCtrl register indicate the action to be taken whena 1

4–284.23 ResetA low on RSINL causes the TCM4300 internal registers to assume their reset values. The power-on resetcircuit also causes internal reset.

4–294.24 Microcontroller InterfaceThe microcontroller interface of the TCM4300 is a general purpose bus interface (see Table 4–24) whichensures compat

4–304.24.2 Mitsubishi Microcontroller Mode of OperationWhen the microcontroller type select MTS1 and MTS0 inputs are held high and low, respectively,

4–31Table 4–28. Microcontroller Interface Connections for Motorola Mode (16 bits)TCM4300TERMINALMICROCONTROLLER TERMINALMTS1, MTS0 Tie to logic levels

4–32

5–15 Mechanical Data5.1 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK4040149/A 03/9550260,13 NOMGage Plane0,250,450,750,05 MIN0,27512575112,00 TYP0,1776100SQ

IMPORTANT NOTICETexas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductorproduct or service withou

vList of IllustrationsFigure Title Page3–1 MCLKOUT Timing Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viList of TablesTable Title Page4–1 TCM4300 Receive Channel Control Signals 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 RXIP,

1–11 IntroductionTexas Instruments (TI) TCM4300 IS-54B advanced RF cellular telephone interface circuit (ARCTIC)provides a baseband interface betwee